[Arm-netbook] Small Pitch BGA Packages

[Bari Ari]

On 01/23/2012 07:35 PM, lkcl luke wrote:
>
>   ... btw, something occurred to me: you notice on that wits-tech
> diagram, ok it's a bit small to see, but there is *just* enough room
> to get a track in between the BGA pins... of 0.8mm pitch.  the pads
> are about 0.3mm or so, and the track width is 0.13mm with a gap of
> 0.13mm either side.
>
>   that is simply flat-out impossible with a 0.4mm pitch BGA grid.
>
>   as a result, any PCB layout that has such tiny pitch is *forced* to
> place vias directly underneath every pin, and to use 8 to 12 layers.
>
>   if you look at hardkernel's 43x25mm postage-stamp PCB, the one that
> they put an exynos4210 on, it's POP but they _still_ had to use 12
> layers, which is mad.
>
>   so i think someone has been reaally thinking hard about the design of
> the allwinner a10: you don't make it possible to put DDR3 RAM within
> 1cm of a CPU only using 6 layer PCBs by accident :)
>
>
Sure they planned it. You optimize pinout for breakout and routing with 
the fewest amount of vias.

The way you achieve breakout with smaller pitch is by using 75um trace 
and space.