[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur
<richard.wilbur at gmail.com> wrote:

>>>  I'm interested to see what
>>> holes/voids and connections the power and ground planes have.
>>
>>  there are *no* connections on the GND planes.  the power plane (and
>> GND layers) interestingly have done a full surround on the HDMI vias.
>> remember i had to separate them by an unusual distance.
>
> What clearance to the fill do you have on the HDMI differential signal
> vias on layer 3, as opposed to 2, 4, and 5?  I see it leaves a void on
> layer 3 but not on layer 4 (or presumably 2 or 5).

 yehyeh.  to be honest: i don't know exactly.  or, i worked it out a
long while ago, and can't remember precisely what it was.

>>> What are the names of the power pins on the A20?  What voltages do you
>>> supply it?
>>
>>  1.1, 1.25, 2.5 and 3.3v.
>>
>>>  (Are any of them Vdiff+/-, e.g?)
>>
>>  no.
>
> Good to know.  Thanks.
>
>>> I'm interested in
>>> tracking down the power supply pins for the differential HDMI signals
>>> as that is where our return path for common-mode signal has to go.
>>
>>  there's no specific power pin for HDMI.  the GND pins are grouped in
>> with a whole stack of other GND pins, there's absolutely no way it's
>> practical to get a special GND plane to it: the board is extremely
>> full already.
>
> I'm not looking to provide any special connection to the power or
> ground pins.  I just want to make sure we don't obstruct the return
> current path any more than necessary on its way from bottom reference
> ground plane (layer 5) to top reference ground plane (layer 2) to the
> power supply pins of the differential drivers:
> 1.  ground plane (layer 2) via to SoC ground pin land (layer 1)
> 2.  ground plane (layer 2) via to power supply decoupling capacitor
> ground land (layer 1), through decoupling capacitor to land on power
> supply trace (layer 1), through trace to SoC power supply pin land
> (layer 1).
>
> The goal is to avoid unnecessarily impeding this return current path.
> I'm trying to avoid making the path >~200mil and putting any major
> obstruction (like a huge layer void) in the way.

 ok - i think i understand.  the distance from the first set of vias
to the nearest decoupling capacitors is 180mil.  those are all at the
centre of the A20 processor.

>>> I've read a little (not nearly as much as I'd like, but I lack time)
>>> about using a taper to match impedance differences while minimizing
>>> the reflection coefficient.[*]  I'm thinking we can use it at both
>>> ends of this layout to great advantage.  We taper from 5mil clearance
>>> around the A20 on layer 1 to 15mil clearance on layer 6.  Later we
>>> taper from 15mil clearance to whatever the closest copper is at the
>>> ESD and connector lands.
>>
>>  that's something that it would be helpful to have a rough diagram,
>> even if it's hand-drawn [but see below: i think i understand it]
>
> Once I figure out the frequency => characteristic taper length
> situation I'll try to send a drawing and/or image.  In the meantime
> I've been looking at [*].

 ooo wow fascinating.

 hmmm... a bit too much to implement though.  PADS can't really
conveniently handle that kind of drawing (ok it can but it's a
complete fricking pain.  you're limited to 45 degree angles, and the
mouse-drag is.. erratic in what it decides to allow you to move ).

>>> Is the closest copper on layer 1, around the A20, 5mil from the HDMI
>>> differential signals?
>>
>>  yes.  everything's 5 mil design rule.
>>
>>> What is the distance to the closest copper to the HDMI signals at the ESD lands?
>>
>>  5 mil
>>
>>> What is the distance to the closest copper to the HDMI signals at the
>>> connector lands?
>>
>>  5 mil
>>
>>> (I'm guessing in both cases it is likely the neighbouring lands.  Is
>>> that correct?)
>
> In retrospect I didn't phrase those questions sufficiently clearly.
> Let me try again.

 sorry!

> I understand that we are using a 5mil design rule clearance for the
> whole board.

 except for the board edge, yes.

> We have attempted to impose an additional requirement on
> the differential pairs for most of their length that the traces of the
> pair be 5mil from each other but at least 15mil from anything else
> (including other pairs).  What I'm curious about is what copper
> violates this additional requirement that can't be moved, where is it,
> and how close does it actually come?

 ah.  ok.  it's components.  so, the EMI components, and the VIAs.
and if the hand-drawn keepout isn't quite the right distance.    ah.
and IPSOUT (main power DC line) which i've just adjusted to be outside
the 15mil boundary.

 and... from the A20's pins: i put a GND trace round the back of the
VIAs because the next row up includes all the USB signals.  i didn't
feel comfortable leaving that without a separation (again, 5mil
clearance).

> If we move the violating copper out to the 15mil boundary, that's
> great:  problem solved.  If we can't (or would really rather not),
> then let's consider where it is along the signal path, how close it is
> to the differential signals, and what net (signal) it is.
>
> 1.  When in the signal path can we open up from 5mil to 15mil?
>
> If that is part way down the first signal vias then we can try scaling
> the keepouts on our way through the board.  From what I've seen, it
> looks like we have to get past sorting the signals out into pairs on
> layer 6 before we have room to do more than 5mil to foreign copper.
> Is that your understanding?

 no - that whole bottom area coming out from the A20 pins, on layer 1
is completely clear except for the GND vias which are staggered in
between where they (immediately... 60 mil...) transition to layer 6.

 on layer 6 they're clear of copper as well.

> 2.  When do we need to scale back down to 5mil?
>
> Is that at the signal vias for the two pairs that jump first to layer
> 1 for ESD?  Or is it at the ESD lands?

 that sounds like a question you're asking yourself :)

>>> What is the minimum frequency we will be running the HDMI at?  (With
>>> version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
>>> on each data line.  Thus I would expect good edges if we design for
>>> harmonics of 34GHz.;>)
>>
>>  :)  1920x1080p60.  honestly though if it works at 1280x720p60 i'll be happy.
>
> Again I wasn't clear enough with the question--I misled you by
> mentioning the highest clock frequency.  To calculate the length
> characteristic for this taper, I need to figure out the lowest
> frequency (minimum) for which we want it to exhibit this impedance.

 ah: i missed "minimum" rather than "maximum".  ok 640x480 at 30hz is the
lowest possible resolution that people would use...

>>> The idea is we can taper the keepouts on our signal vias near the A20
>>> by the layer and avoid such an abrupt change from layer 1 to layer 6.
>>
>>  i would very much like to have used layer 3 instead of layer 6 for
>> the HDMI signals long straightaway but it is too late now
>
> It would then be stripline (uses 3 layers) instead of microstrip (2
> layers).  Stripline uses over and under reference planes.

 mmfh.  ok understood.

>>  ok i did the taper at the DC3 connector end, and i think i got it
>> reasonably ok at the A20 end.  haven't run flood-fill.  A20 end is a
>> bit of a mess, bit unavoidable.  left side is ok.  right side...
>> because of the immediate turn and the TX2 line...
>
> The fine point of it is there is a particular curve involved in
> Klopfenstein and it requires a length which determines the frequency
> band over which you get the low reflection coefficient.

 yes.  i saw the paper.  that's going to be too complex to do.  i'd
have to construct it by hand in steps, of 45 degrees.  or i can
actually hand-edit the points and enter in numbers... but i have to
create approximate points first (to get a valid non-intersecting
polygon...)

 honestly it's a bit too much hard work.  if i was able to manipulate
these things in e.g. python i'd say "let's go for it", immediately.

> That's why
> I'm trying to figure out what frequencies we care about and then see
> whether we can accommodate the length needed or we just have to make
> an approximation that is better than nothing.

 one step is fine - two or more gets _really_ awkward.

>> so.  i really want to wrap this up, and get the gerbers out.
>>
>>  loootta work... :)
>
> Indeed.  I am trying to reduce the feedback loop delay on this end.

 thx richard.

> Reference:
> [*]  https://www.microwaves101.com/encyclopedias/klopfenstein-taper

 absolutely fascinating.