[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Richard Wilbur]

On Wed, Sep 20, 2017 at 1:57 AM, Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Tue, Sep 19, 2017 at 11:26 PM, Richard Wilbur
> <richard.wilbur at gmail.com> wrote:
>> On Sat, Sep 16, 2017 at 8:23 AM, Luke Kenneth Casson Leighton
>> <lkcl at lkcl.net> wrote:
>>> http://rhombus-tech.net/allwinner_a10/news/
>>>
[...]
>>> l'm including layer 3 as an example of how
>>> the group of HDMI vias that come just out of the A20 punch a large
>>> hole: GND-flooded layers 2 and 5 as well as 4 (power plane) will also
>>> look like that.
>>
>> Could you put a similar snapshot of layers 2, 4, 5 on hands.com (or
>> wherever you think appropriate)?
>
>  they're exactly the same as what you see for layer 3.... except
> entirely full.  ok that's not actually true (i just checked) - do a
> page-refresh on the URL i just added layer 4 image)

Thanks for the image.

>>  I'm interested to see what
>> holes/voids and connections the power and ground planes have.
>
>  there are *no* connections on the GND planes.  the power plane (and
> GND layers) interestingly have done a full surround on the HDMI vias.
> remember i had to separate them by an unusual distance.

What clearance to the fill do you have on the HDMI differential signal
vias on layer 3, as opposed to 2, 4, and 5?  I see it leaves a void on
layer 3 but not on layer 4 (or presumably 2 or 5).

>> What are the names of the power pins on the A20?  What voltages do you
>> supply it?
>
>  1.1, 1.25, 2.5 and 3.3v.
>
>>  (Are any of them Vdiff+/-, e.g?)
>
>  no.

Good to know.  Thanks.

>> I'm interested in
>> tracking down the power supply pins for the differential HDMI signals
>> as that is where our return path for common-mode signal has to go.
>
>  there's no specific power pin for HDMI.  the GND pins are grouped in
> with a whole stack of other GND pins, there's absolutely no way it's
> practical to get a special GND plane to it: the board is extremely
> full already.

I'm not looking to provide any special connection to the power or
ground pins.  I just want to make sure we don't obstruct the return
current path any more than necessary on its way from bottom reference
ground plane (layer 5) to top reference ground plane (layer 2) to the
power supply pins of the differential drivers:
1.  ground plane (layer 2) via to SoC ground pin land (layer 1)
2.  ground plane (layer 2) via to power supply decoupling capacitor
ground land (layer 1), through decoupling capacitor to land on power
supply trace (layer 1), through trace to SoC power supply pin land
(layer 1).

The goal is to avoid unnecessarily impeding this return current path.
I'm trying to avoid making the path >~200mil and putting any major
obstruction (like a huge layer void) in the way.

>> I've read a little (not nearly as much as I'd like, but I lack time)
>> about using a taper to match impedance differences while minimizing
>> the reflection coefficient.[*]  I'm thinking we can use it at both
>> ends of this layout to great advantage.  We taper from 5mil clearance
>> around the A20 on layer 1 to 15mil clearance on layer 6.  Later we
>> taper from 15mil clearance to whatever the closest copper is at the
>> ESD and connector lands.
>
>  that's something that it would be helpful to have a rough diagram,
> even if it's hand-drawn [but see below: i think i understand it]

Once I figure out the frequency => characteristic taper length
situation I'll try to send a drawing and/or image.  In the meantime
I've been looking at [*].

>> Is the closest copper on layer 1, around the A20, 5mil from the HDMI
>> differential signals?
>
>  yes.  everything's 5 mil design rule.
>
>> What is the distance to the closest copper to the HDMI signals at the ESD lands?
>
>  5 mil
>
>> What is the distance to the closest copper to the HDMI signals at the
>> connector lands?
>
>  5 mil
>
>> (I'm guessing in both cases it is likely the neighbouring lands.  Is
>> that correct?)

In retrospect I didn't phrase those questions sufficiently clearly.
Let me try again.

I understand that we are using a 5mil design rule clearance for the
whole board.  We have attempted to impose an additional requirement on
the differential pairs for most of their length that the traces of the
pair be 5mil from each other but at least 15mil from anything else
(including other pairs).  What I'm curious about is what copper
violates this additional requirement that can't be moved, where is it,
and how close does it actually come?

If we move the violating copper out to the 15mil boundary, that's
great:  problem solved.  If we can't (or would really rather not),
then let's consider where it is along the signal path, how close it is
to the differential signals, and what net (signal) it is.

1.  When in the signal path can we open up from 5mil to 15mil?

If that is part way down the first signal vias then we can try scaling
the keepouts on our way through the board.  From what I've seen, it
looks like we have to get past sorting the signals out into pairs on
layer 6 before we have room to do more than 5mil to foreign copper.
Is that your understanding?

2.  When do we need to scale back down to 5mil?

Is that at the signal vias for the two pairs that jump first to layer
1 for ESD?  Or is it at the ESD lands?

>> What is the minimum frequency we will be running the HDMI at?  (With
>> version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
>> on each data line.  Thus I would expect good edges if we design for
>> harmonics of 34GHz.;>)
>
>  :)  1920x1080p60.  honestly though if it works at 1280x720p60 i'll be happy.

Again I wasn't clear enough with the question--I misled you by
mentioning the highest clock frequency.  To calculate the length
characteristic for this taper, I need to figure out the lowest
frequency (minimum) for which we want it to exhibit this impedance.

>> What is the vertical distance from layer to layer in our board stack?
>
>  it's a 6 layer 1.2mm PCB.  if i have actually set the design
> parameters right (rather than just telling the factory manually) then
> the substrates are 1.35mil and the dielectrics 10mil

Good information. Thanks.

>> The idea is we can taper the keepouts on our signal vias near the A20
>> by the layer and avoid such an abrupt change from layer 1 to layer 6.
>
>  i would very much like to have used layer 3 instead of layer 6 for
> the HDMI signals long straightaway but it is too late now

It would then be stripline (uses 3 layers) instead of microstrip (2
layers).  Stripline uses over and under reference planes.

>> Likewise, we can change the geometry of the keepout as we approach the
>> ESD lands and finally the connector to likewise ease the transition.
>
>  okaaaay i think i understand what you mean.

[...]
>> There is one place in layer 6 where the space between the CLK pair and
>> the adjacent data pair looks like it exceeds 35mil for a non-trivial
>> distance.  I think we could safely reintroduce a ground trace
>> connecting the 2 or 3 vias in that space and thus keep the environment
>> close to 15mil from differential trace to either ground or
>> neighbouring signal.
>
>  good call. i know exactly where you mean.  refresh URL and see new image.
>
>   http://rhombus-tech.net/allwinner_a10/news/

Looks good.  Thanks.

>  ok i did the taper at the DC3 connector end, and i think i got it
> reasonably ok at the A20 end.  haven't run flood-fill.  A20 end is a
> bit of a mess, bit unavoidable.  left side is ok.  right side...
> because of the immediate turn and the TX2 line...

The fine point of it is there is a particular curve involved in
Klopfenstein and it requires a length which determines the frequency
band over which you get the low reflection coefficient.  That's why
I'm trying to figure out what frequencies we care about and then see
whether we can accommodate the length needed or we just have to make
an approximation that is better than nothing.

> so.  i really want to wrap this up, and get the gerbers out.
>
>  loootta work... :)

Indeed.  I am trying to reduce the feedback loop delay on this end.

Reference:
[*]  https://www.microwaves101.com/encyclopedias/klopfenstein-taper