[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Luke Kenneth Casson Leighton]

On Thu, Oct 26, 2017 at 5:36 PM, Richard Wilbur
<richard.wilbur at gmail.com> wrote:
> My wife was sick last week so I spent more quality time with my
> daughters taking them to appointments, working with them on their
> studies, et cetera.

 not a problem richard.  as you may have (or probably more sensibly
didn't) see, i'm taking the opportunity to focus on shenzhen maker
faire and the two 3d printers, plus sensor boards, plus low-cost
STM32F-based arduino-due board, plus RD3D (a major upgrade to RAMPS)
and so on.

> I'm working on the geometry of the taper for this afternoon, but first
> a few questions to clarify some points.

 cool.

>>  track width changes... yyeah... 4 mil would be the thinnest tracks on
>> the entire board, i'm reluctant to do it but we can do it if
>> necessary.
>
> I think we can get away without much of the special considerations we
> are spending on this and it will probably work just fine at HDMI v1.4
> but moving up to higher clock speeds with the later versions will
> likely require more care.

 later versions are *never* going to go to HDMI 2.0 speeds... because
there will never be a version of the A20 which can do HDMI 2.0 speeds.
basically for an upgrade to HDMI 2.0 that means using a totally new
SoC, that means completely starting from scratch with a completely and
entirely new PCB layout.

> That said,
> 1.  do you have a picture of the HDMI layout you referred to which is
> known to have worked?

 ha.  very funny joke.  as in, it's so bad that you'll laugh
hysterically at how completely they failed to follow the HDMI design
rules.  in fact, i am sure that they actually knew them... just so as
to be able to *deliberately fail* to obey EVERY SINGLE ONE OF THEM,
because it is statistically significant that they actually failed to
follow all of them, 100%.

  it's spread out on 3 layers: CLK goes onto layer 6, TX0-2 on layer
3, there's not even the slightest effort to provide GND separation,
HSCL and so on are routed within 5 mil of the diff-pairs, there's
absolutely no respecting diff-pair via spacing whatsoever, intra and
inter pair vias are separated by 5mil, absolutely no GND vias nearby
of any kind, and the pairs don't even length-match, not inter or
intra.  at all.  the ESD protection was all on layer 6, meaning that
there were totally unnecessary via jumps from layer 3 to layer 6 and
then to layer 1 just to get to the ESD and then back to the connector,
all within about... 1.5mm of each other.

 basically the tracks were treated as if they were ORDINARY tracks,
jammed in tightly together because of space restriction down that edge
of the board.

 there's absolutely no chance it would pass EMI... but incredibly it
did actually get 1080p30 out the connector without any kind of visual
artefacts or failures to display.  stunning, really.

 i'm actually too embarrassed to send you any kind of pictures as it
will only put you into shock.  oh - when i say "no ground vias" i mean
ABSOLUTELY NO ground vias whatsoever (either side), even though the
HDMI tracks travel within 25 mil of the board edge for the entire
distance.

 the rule has appeared to be: take everything we've done here.... and
do the total opposite.


> I'm working under the assumption that we can leave the board
> fabrication parameters alone (stack thickness, smallest trace,
> smallest gap) and still make a working HDMI transmitter.

 if the above is anything to go by, it should be pretty clear that you
can get away with a hell of a lot more than expected.  HDMI 2.0
absolutely no chance, but 1.4?  seems to be... pretty tolerant.
amazingly.


> 2.  Does Mentor Graphics give any documentation to explain the
> provenance of the impedance numbers it reports from PADS layout?

 not that i've ever looked for it, but i can make some guesses.  it's
a lot LOT simpler than you're expecting.  there's absolutely no
consideration taken of neighbouring GND on the same layer
*whatsoever*, for example.


> I am somewhat surprised to hear that our impedance is higher than we
> calculated with the TI equations--especially since we have several
> incursions within the guidelines they suggested.

 the numbers have absolutely nothing to do whatsoever with
neighbouring tracks.  as in: the fact that neighbouring tracks exist -
or not - or the fact that there may - or may not - exist any copper
pour within any distance of any kind, to any part of any track, is
COMPLETELY AND UTTERLY IGNORED.

 the only factors taken into consideration appear to be board
thickness, track length, and distance to any plane SPECIFICALLY marked
as "GND".

 i tested this out by changing the thickness of the substrate between
Layer 1 (TOP) and Layer 2 (GND) and then compensating for that change
by matching it in LAYER 3 (GND) and Layer 4 (POWER).  the result was:
the reported impedance of the HDMI tracks changed.

 so we *can* actually adjust the impedance by altering the stack: i
know a fab house that has an extremely good engineer who knows how to
do that just from the gerbers alone, but i don't have access to him
any more.


>  I expected to be on
> the low side, not the high side, of what we designed for.

 you may be believing that i have access to "Hyperlinx" which is the
Signal Integrity / Simulation package.  that CAN - as best i know - do
the kinds of impedance analysis that you're expecting / believing that
is reported.

 i do NOT have access to that package.  the impedance value reported
by PADS DOES NOT in ANY WAY take into account the nearby copper.  not
even when you actually run the flood-fill.  it's simply too
complicated to do (requires Signal-level electronics Simulation) and
that's just not part of the PADS program: it's part of Hyperlynx.


> Thus my
> initial reaction that the 89Ω value sounded more like the differential
> impedance which had sagged a bit (from ~110Ω) under the pressure of
> close copper.

 nope.  not at all.  under no circumstances is PADS (on its own)
capable of taking into account the closeness of any copper (pour or
tracks). in the reported impedance value it COMPLETELY ignores ALL
copper and ALL nearby tracks, taking into account ONLY those three
parameters: length, width, and distance to any GND plane(s).

> So if the impedance number from PADS is to be useful we really need to
> know what it is measuring.  If it is single-ended, we are high and
> take measures to reduce it such as bringing ground fill closer to
> traces.

 it's single-ended, and has absolutely nothing whatsoever to do with
any copper on the same layer, whatsoever.

> 3.  How far do the differential pairs travel in the northeast
> direction after turning up from the bottom of the board?  (Dimension
> 'A' in the diagram below.)

 5.6mm

> 4.  How far do the TX0 traces travel after turning northeast from the
> bottom of the board before they have to turn due north to avoid those
> ground vias?  (Dimension 'B' in the diagram below.)

 1.3mm.

 btw.. *sigh* one very important bit of info: the layer stack
parameters i double-checked, i wasn't confident that they were for a
1.2mm board, and it's good that i checked.

 https://www.quick-teck.co.uk/TechArticleDoc/4138811771353606590.pdf

 the pre-preg distance is supposed to be 0.2mm not 0.254 to create a
standard 1.2mm 6-layer stack.  i had 0.254 which is for a 1.6mm.
whoops.

 so the actual impedance reported - now that i've modified the design
rules for the stack to match 1.2mm total height, are 81 ohms.

 sorry!

l.