[Arm-netbook] open risc v question:

[zap]

On 12/29/2017 12:53 AM, Luke Kenneth Casson Leighton wrote:
> On Thu, Dec 28, 2017 at 10:33 PM, zap <calmstorm at posteo.de> wrote:
>> Are the shakti processors arm based
>  HELL no!!!  why do you think they tried to bribe him to shut the
> project down!!  oops did i mention that on a public mailing list?
> mwahahaa
Interesting, never knew that. and yeah, probably not the best idea but
meh...
>
>>  for the architecture or some new
>> architecture or a different one.
>  RISC-V.  they are however doing it as a complete reimplementation,
> using a design system that's based on.... Haskell :)  it's like
> myhdl.org (which is python) except it's Haskell -> Verilog.  the
> advantage of that is that it's REALLY quick to write stuff in... and
> it has the advantage of being *formally mathematically provable*.
> unlike Chisel, which is what the rocket-chip is based on.
>
>  also they're going for an 8 stage pipeline not 5, so the max speed is
> around 2.5ghz where rocket-chip gets around 1.5ghz in 40nm,
>
>  http://bitbucket.org/casl
>
Risc-V hmm... interesting. I know arm is based off of a Risc chip so
that's why I wondered...

Any idea when these processors will be sold?
>> I believe you said the M class is supposed to be less than 1W. Which
>> sounds absolutely insane. Dunno how they will do that, but it looks
>> interesting especially considering the blazing speed it says on the charts.
>  120mW per core it's easily achievable.  i mentioned that the EOMA68
> power budget is 2.5 watts and madhu laughed: do the math, you can get
> 16 SMP cores into 2.5 watts :)
Wow... that's freakin awesome.  Any idea when such a processor will be
implemented into the eoma68 standard?
> l.
>
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