[Arm-netbook] libre 64-bit risc-v SoC

[ryan]

On 04/28/2017 05:56 PM, Bill Kontos wrote:
>
> Out of curiosity has anyone ever attempted to prototype a hardware 
> block based on evolution principles? Doing it on an fpga is probably a 
> bad idea since we wont be able to implement the results in more copies 
> but this could potentially also happen in a software simulation where 
> the input and output interfaces of the hardware block are pre defined
>
> <snip>

I suspect that without having the feature of it being an instruction set 
that only works on that one chip due to it exploiting the quirks of the 
chip, some efficiency would be lost.

I'm imagining a system where traditional silicone grooms many FPGAs, 
each with a dedicated task, and the system is provided with some 
known-good instruction sets that work, but only slowly. So then either 
the OEM or the user sets up their fancy new system, and one of the steps 
is to plug it in and run a setup program for anywhere from a few hours 
to a couple of days which iterates the instructions to improve 
efficiency, then they can begin to use their system.

As for using this method in a software simulation, I wouldn't be 
surprised if some chip manufacturers already do that for certain 
sections of the chip, even if its only during the early design faze. I 
would imagine the software guiding the evolution could be instructed to 
cull anything that isn't working with binary, thus allowing human 
engineers/programmers to more easily reverse engineer the instruction 
set and further edit it.



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