[Arm-netbook] libre 64-bit risc-v SoC

Bill Kontos vkontogpls at gmail.com
Fri Apr 28 23:56:27 BST 2017


Out of curiosity has anyone ever attempted to prototype a hardware block
based on evolution principles? Doing it on an fpga is probably a bad idea
since we wont be able to implement the results in more copies but this
could potentially also happen in a software simulation where the input and
output interfaces of the hardware block are pre defined
On Apr 28, 2017 2:47 PM, "mike.valk at gmail.com" <mike.valk at gmail.com> wrote:

>
>
> 2017-04-28 13:23 GMT+02:00 Luke Kenneth Casson Leighton <lkcl at lkcl.net>:
>
>> On Fri, Apr 28, 2017 at 11:29 AM, mike.valk at gmail.com
>> <mike.valk at gmail.com> wrote:
>
>
>> > The problem is MUXing all modes to a single output. New Apple laptops
>> have
>> > USB-C but not all ports support all functions.
>> >
>> > Perhaps a bit of FPGA could be the key?
>>
>>  yeah.
>>
>> > Ethernet over UCB-C is still being discussed. So the FPGA might be
>> handy to
>> > have when/if that mode is materialized.
>> >
>> > A bit of FPGA would be nice to have anyway. Media codecs keep on
>> changing
>> > and would extend the life of the SoC.
>>
>>  at the expense of power consumption.
>
>
> If you're trying to trans-code something that you don't have a
> co-processor/module for you're forced to CPU/GPU trans-coding. Would a FPGA
> still be more power huns gry then?
>
> I think/hope FPGA's are more efficient for specific tasks then CPU/GPU's
>
> We can always have evolution create a efficient decoder ;-)
> https://www.damninteresting.com/on-the-origin-of-circuits/
> http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.
> 50.9691&rep=rep1&type=pdf
>
>
>
>
>
>
>
>>
>
>
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