[Arm-netbook] Another chip to consider for a future EOMA product

[luke.leighton]

On Fri, Oct 4, 2013 at 1:57 PM, Stéphane Goujet
<stephane.goujet at wanadoo.fr> wrote:
> Le Fri, 4 Oct 2013 12:25:58 +0100,
> "luke.leighton" <luke.leighton at gmail.com> a écrit :
>
>> On Fri, Oct 4, 2013 at 10:26 AM, Stéphane Goujet
>> <stephane.goujet at wanadoo.fr> wrote:
>> >>  * DDR RAM: 2x 8-bit (only 16-bit Data) and 16 address lines.
>> >   I have to say I really do not understand why it supports x8 chips
>> > only and not x16. I must miss a point.
>>  because it's ultra-low-power.  at 400mhz (800mhz DDR3) you'd be
>> looking at only... what... 175mA?  i think *finger-in-air* 32-bit DDR3
>> ICs @ 400mhz use around 350mA.
>
>   What I meant was 1x16, not 2x16, sorry for the misunderstanding. They
> insist on saying it supports 2x 8-bit wide chips and nothing else, but I
> cannot see why we could not use a single 16-bit wide chip (much easier
> to route).

 oh right.  yes, i see.  ahh... i think it's going to depend on how
they implemented the DDR3 controller.  let's think for a moment...
intel have a habit of using their own "stuff", not licensing other
peoples' industry-standard hard macros, and this is their first real
foray into anything below 32-bit memory buses [at least for 2 decades,
it is!]

 so whereas everyone else would license a DDR3 hard macro that
conformed to the specifications and allowed flexibility (because
otherwise as a hard macro licenser they'd get no customers), there's
no guarantee that intel have bothered to implement anything other than
what they've said that's been implemented.

l.