[Arm-netbook] Allwinner outsells Intel

[joem]

On Thu, 2013-05-09 at 19:19 +0600, Roman Mamedov wrote:
> On Thu, 9 May 2013 13:03:49 +0000
> joem <joem at martindale-electric.co.uk> wrote:
> 
> > Hmm...
> > 
> > The shortest reply I can give you is that as EEs we
> > make our own buses, drivers and protocols.
> 
> Yep, and the thing is, you don't make or rewire ASICs, what's inside the A10
> you can't change, it doesn't support SMP and you can't magically add that.
> 
> In theory you could kludge something around it in a cluster-like architecture,
> but for it to have any kind of performance at all, an additional ASIC may be
> required;

You are going somewhere I do not wish to follow - HPC - its a completely
different subject.

Lots of IO port pins are available, and first target for me at least
is simple low cost assembly of images in a conveyor to replace
proprietary graphics cards. So if product has to play video and do some
simple game like functions, then copy and paste two CPUs, interconnect
some IO pins to compose images and transfer images between CPUs to
destination CPU that has the LCD. At $20 per A10 chip + 1GB RAM +
components, no one batter an eye lid if the solution works.


> ...and even THEN it  will be highly different from "just a multi-core
> processor", it will probably look like several independent nodes with at best
> shared access to a RAM area, and this will help you only in specialized
> computing tasks specifically programmed for it (or via some more standard HPC
> layer like OpenMPI).
> 
> Not as simple as copypasting some KiCAD around.

As I say wait and see.
As the copy/paste experimentation begins, new techniques will evolve.
KiCAD for example is all text based, so in theory it is possible
to write a script where you enter number n of CPUs, and out pops
a fully formed text file with n CPUs fully wired up!!!!!!!!! :)
There are already scripts available for various features and
functions already. Its again a case of wait and see, or even
participate and do!