[Arm-netbook] AllWinner F20/A10 - SDRAM initialisation

[sysfwlab]

Hello Everybody,

Related to my porting project "uboot for sun3i",  i'm able to manager my 
SDRAM now and it's a good thing but my sdram init procedure is not very 
elegant. Can someone tell my if it's a common behavior to need to 
read/write'n compare like 'brutus' to wait SDRAM be intialized ?

Here is a working exemple with th SDRAM PLL bypassed (so sdram is 
clocked by HOSC like CPU in my case 24MHz).
After doing this i can do successfully read/write on the entiere SDRAM 
area (107374183 bytes  on F20)

/* Init sdram */
u32 *reg=(u32*)(SUNXI_CCM_BASE+CCM_O_SDRAM_PLL_R);
sr32(reg,10,2,3);    // Bypass + Enabled
sr32(reg,15,1,1);    // Special Gate
reg=(u32*)(SUNXI_CCM_BASE+CCM_O_AHB_GATE_R);
sr32(reg,13,1,1);    // SDRAM AHB Gate

/* Badly wait for sdram be initialized */
u32 sdt;
do{
     writel(0xbeef,(void*)SUNXI_SDRAM_START);                // Write 
'0xbeef' at start of SDRAM
     for(sdt=0;sdt<1000;sdt++){ }                                     // 
Wait a little (Bad tempo)
     
putc('.');                                                                         
// Let me know on serial
}while( readl((void*)SUNXI_SDRAM_START)!=0xbeef );   // Continue during 
'0xbeef' is not persistant...
                                                                                          // '0xbeef'  it's not a special token here we can use 0x1234 or other...



Do you know an other way to know when sdram is initialized ?
(I try to check the "selfrefresh status" bit but it's already disabled 
at startup)
Do you think this way can destroy controller in future ?

Thanks in advance

Bin