[Arm-netbook] [review] SoC proposal

lkcl luke luke.leighton at gmail.com
Wed Feb 8 19:58:44 GMT 2012


folks, hi,

i've not mentioned this before, publicly, but some time last year when
this initiative was still being considered we were finding it so
ridiculously difficult to find cooperative CPU companies that we gave
serious consideration to putting a deal together to create a new
(entirely software-based) SoC that would be entirely FSF-Endorseable
as it would be entirely software-programmable.

based around something like the ARC 32-bit RISC core (which was a hell
of a lot better than ARM's offerings at the time), the idea was to put
at least 4 of them down in 28nm, where they would quite happily run at
at least 1.5ghz.

the problem was that ARC's RISC core design wasn't SMP capable, and
the team behind it didn't feel comfortable doing SMP cache coherency.
we _did_ come up with a mad and very simple scheme to do cache
coherency as a software interrupt (similar to how MMU page-swapping is
done) and even discussed it on LKML thanks to alan cox and some input
from another guy from intel, it turns out to have been a workable
scheme.

... but, we didn't pursue it.

some time last month i went "hang on a minute, maybe now's a better
time" so i've done a draft of the interfaces (DDR3 RAM will be
included)  the number of pins required is surprisingly low, which will
get the cost down.

i'd therefore greatly appreciate some help reviewing the pinouts.  the
company that i've found that has an alternative 32-bit RISC core not
only has SMP cache coherency already done, but also they have an
absolutely amazing set of Instruction extensions, including DSP,
Audio, Video, Base-band (for RF handset processing) and much more.
the plan is, therefore, to target this CPU at a very very wide range
of markets, based on it having:

* 8 CPUs at 1.2ghz or above
* SMP Cache Coherency
* 32-bit DDR3 1333mhz RAM (with a 2nd version having 2 DDR3 interfaces)
* virtually everything software-programmable (with the exception of
CABAC decode)

meaning that it will do 3D graphics _and_ 1080p Video entirely in
software.  the interfaces i've selected so far will include:

* HDMI Out _and_ In
* 24-pin RGB/TTL
* 2-channel LVDS
* 2 PCIe (2-lane each)
* USB-OTG, USB-2 and USB-3
* SATA-3
* NAND controller (8-bit with 4-way CS)
* 3 SD/MMC interfaces
* 3 SPI interfaces
* 3 UARTs, 3 IIC interfaces, CAN-Bus, 2 PS/2, Touchscreen, 3 PWMs
* 2 MPEG Transport Stream Interfaces
* Smartcard Interface

that means that it could be used in at least the following products:

* Laptops, Netbooks, Tablets, Desktops, PCs, NAS-Boxes
* PVRs, TVs, Set-Top Boxes, Satellite Decoders
* Smartphones, Base Stations, GNU/Radio SDR Products

bearing in mind that this will be out some time in middle of 2013, if
it's started soon, i could reallly do with some help reviewing the
interfaces and capabilities, to make sure i've got it right.

tia,

l.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: cpu-Overview.pdf
Type: application/pdf
Size: 42293 bytes
Desc: not available
Url : http://lists.phcomp.co.uk/pipermail/arm-netbook/attachments/20120208/8dac03b3/attachment-0001.pdf 


More information about the arm-netbook mailing list