[Arm-netbook] DDR3...

[Gordan Bobic]

On 01/05/2012 10:49 PM, lkcl luke wrote:
> whoooooooEE :)
>
> http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/4242Gb_DDR3_SDRAM.ashx
>
> does aaaanybody find these paragraphs a tad scary?  memory controller
> sends out ping-queries to each RAM IC, works out the delay and then
> uses that in future read/writes.  aaaaah!
>
> For better signal integrity, DDR3 SDRAM memory modules have adopted
> fly-by topolo-
> gy for the commands, addresses, control signals, and clocks. Write
> leveling is a scheme
> for the memory controller to adjust or de-skew the DQS strobe (DQS,
> DQS#) to CK rela-
> tionship at the DRAM with a simple feedback feature provided by the
> DRAM. Write lev-
> eling is generally used as part of the initialization process, if
> required. For normal
> DRAM operation, this feature must be disabled. This is the only DRAM
> operation where
> the DQS functions as an input (to capture the incoming clock) and the
> DQ function as
> outputs (to report the state of the clock). Note that nonstandard ODT
> schemes are re-
> quired.
> The memory controller using the write leveling procedure must have
> adjustable delay
> settings on its DQS strobe to align the rising edge of DQS to the
> clock at the DRAM pins.
> This is accomplished when the DRAM asynchronously feeds back the CK
> status via the
> DQ bus and samples with the rising edge of DQS. The controller
> repeatedly delays the
> DQS strobe until a CK transition from 0 to 1 is detected. The DQS
> delay established by
> this procedure helps ensure tDQSS, tDSS, and tDSH specifications in
> systems that use
> fly-by topology by de-skewing the trace length mismatch. A conceptual
> timing of this
> procedure is shown in Figure 47.

That sounds terrifying. It sounds to me rather like OC-ing and declaring 
something stable just because the machine POSTs.

Gordan