Judging by the info on the webpage -- it's being done by the RasPi folks, with assistance from Bunnie Huang and Google (boy, having those two in one room should be fun)... interesting that one of the three main team members appears to mostly be a financial contributor.
My read is admittedly cynical (it's a well-learned behavior pattern of mine) that the differing opinions will turn this into a flash-in-the-pan via vision/viewpoint arguments that tear it to bits... but we shall see. Should be fun to watch, in any event...
On Thu, Aug 7, 2014 at 12:05 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net
wrote:
On Thu, Aug 7, 2014 at 4:33 PM, Guillaume FORTAINE gfortaine@live.com wrote:
wow cool!
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2014-08-07 16:33 Guillaume FORTAINE:
Is this any different in concept from OpenRISC 1000 (or1k)?
http://opencores.org/or1k/Main_Page
I do not know much about hardware or production details, if planned at all at this stage.
With or1k we have already ~6.6k architecture-dependent (that have to be compiled) source packages from Debian available, and being updated whenever they are uploaded to Debian unstable. These are readily available for simulations and for people who can synthesise this in a FPGA.
http://wannabuild.cmd.nu/architecture.php?a=or1k&suite=sid
Cheers. -- Manuel A. Fernandez Montecelo manuel.montezelo@gmail.com
On Thu, Aug 7, 2014 at 6:58 PM, Manuel A. Fernandez Montecelo manuel.montezelo@gmail.com wrote:
2014-08-07 16:33 Guillaume FORTAINE:
Is this any different in concept from OpenRISC 1000 (or1k)?
by a long margin: yes. OpenRISC i don't believe was ever planned to run at the kinds of speeds that RISC-V plans to operate at. http://riscv.org/download.html#tab_rocket shows that they are producing benchmarks for operation at 1ghz. the RISC-V architecture appears to be designed as 64-bit from the ground up, and there also appear to be room for instruction set extensions as well: http://riscv.org/faq.html#simd
With or1k we have already ~6.6k architecture-dependent (that have to be compiled) source packages from Debian available, and being updated whenever they are uploaded to Debian unstable. These are readily available for simulations and for people who can synthesise this in a FPGA.
http://riscv.org/getting-started.html
full toolchain, port of qemu, and an FPGA port.
no debian port yet though. biiit early for that :)
l.
2014-08-07 20:02 Luke Kenneth Casson Leighton:
On Thu, Aug 7, 2014 at 6:58 PM, Manuel A. Fernandez Montecelo manuel.montezelo@gmail.com wrote:
2014-08-07 16:33 Guillaume FORTAINE:
Is this any different in concept from OpenRISC 1000 (or1k)?
by a long margin: yes. OpenRISC i don't believe was ever planned to run at the kinds of speeds that RISC-V plans to operate at. http://riscv.org/download.html#tab_rocket shows that they are producing benchmarks for operation at 1ghz. the RISC-V architecture appears to be designed as 64-bit from the ground up, and there also appear to be room for instruction set extensions as well: http://riscv.org/faq.html#simd
I do not know if there's an issue with speed limits of or1k, and it's true the part about 64 bits.
There's more info here, and and interesting discussion in comments, look for example the comments from Jeremy Bennett comparing both:
http://www.eetimes.com/author.asp?section_id=36&doc_id=1323406
In short, other than the possibility that physical chips available for purchase might be more likely from lowrisc, there do not seem to be many technical differences.
With or1k we have already ~6.6k architecture-dependent (that have to be compiled) source packages from Debian available, and being updated whenever they are uploaded to Debian unstable. These are readily available for simulations and for people who can synthesise this in a FPGA.
http://riscv.org/getting-started.html
full toolchain, port of qemu, and an FPGA port.
no debian port yet though. biiit early for that :)
OpenRISC or1k has all of this as well, that's the reason why the Debian port was able to start.
I don't know how the quality and completeness of toolchain/qemu/etc implementations compare, though.
-- Manuel
http://linuxgizmos.com/project-aims-to-build-fully-open-soc-and-dev-board/
----------------------------------------
Date: Fri, 8 Aug 2014 18:58:50 +0100 From: manuel.montezelo@gmail.com To: arm-netbook@lists.phcomp.co.uk Subject: Re: [Arm-netbook] LowRISC : a CPU open-sourced down to the silicon level, based on RISC-V architecture
2014-08-07 20:02 Luke Kenneth Casson Leighton:
On Thu, Aug 7, 2014 at 6:58 PM, Manuel A. Fernandez Montecelo manuel.montezelo@gmail.com wrote:
2014-08-07 16:33 Guillaume FORTAINE:
Is this any different in concept from OpenRISC 1000 (or1k)?
by a long margin: yes. OpenRISC i don't believe was ever planned to run at the kinds of speeds that RISC-V plans to operate at. http://riscv.org/download.html#tab_rocket shows that they are producing benchmarks for operation at 1ghz. the RISC-V architecture appears to be designed as 64-bit from the ground up, and there also appear to be room for instruction set extensions as well: http://riscv.org/faq.html#simd
I do not know if there's an issue with speed limits of or1k, and it's true the part about 64 bits.
There's more info here, and and interesting discussion in comments, look for example the comments from Jeremy Bennett comparing both:
http://www.eetimes.com/author.asp?section_id=36&doc_id=1323406
In short, other than the possibility that physical chips available for purchase might be more likely from lowrisc, there do not seem to be many technical differences.
With or1k we have already ~6.6k architecture-dependent (that have to be compiled) source packages from Debian available, and being updated whenever they are uploaded to Debian unstable. These are readily available for simulations and for people who can synthesise this in a FPGA.
http://riscv.org/getting-started.html
full toolchain, port of qemu, and an FPGA port.
no debian port yet though. biiit early for that :)
OpenRISC or1k has all of this as well, that's the reason why the Debian port was able to start.
I don't know how the quality and completeness of toolchain/qemu/etc implementations compare, though.
-- Manuel
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Christopher Havel -
Guillaume FORTAINE -
Luke Kenneth Casson Leighton -
Manuel A. Fernandez Montecelo