HDMI Layout Notes for EOMA68 Cards by Richard Wilbur
Timing
Now that we have a speed of propagation, let's figure out the timing constraints imposed by the HDMI standard to the level we plan to support--v1.4. The standard doesn't seem to be freely available so, thankfully, several manufacturers mention various timing constraints in their documentation. The maximum pixel clock frequency is revealed in Toradex' design guide.
Max Frequency: (HDMI v1.0-1.2a) 825 MHz (165 MHz pixel clock) (HDMI v1.3-1.4) 1.65 GHz (340 MHz pixel clock)[3]
For a transmitter, many impedance improprieties (mismatches) can be forgiven in the first quarter-wavelength of propagation.
T(Pixel) = 1/(pixel clock) = 1/(340MHz) = 2.94ns wavelength = velocity * period = 150um/ps * 2940ps = 441mm = 17400mil quarter wavelength = wavelength / 4 = 4350mil
So, while we will try to match the impedance of our traces (transmission lines) as carefully as possible to the characteristic impedance specified for the cable, until we get to 4.3 inches from the signal source the line driver should be able to squash most reflections on the leading edges (first quarter wavelength). Impedance still matters for proper signal levels, but more in the bulk sense.
The problem we will first turn our attention to, then, is that of skew (differences in signal arrival time) usually most noticeably caused by differences in trace length. Several goals are outlined in the literature I reviewed: skew between the clock pair and any data pair, skew between any two pairs (both of these fall under what I would call "Inter-pair Skew"), and skew between the traces of a particular pair ("Intra-pair Skew").
Inter-pair skew: (Requirements for HDMI v1.4) clock-data skew: Δt <150ps[3] => Δl < v * Δt = 22mm ~= 870mil T(Pixel) = 1/(pixel clock) = 2.94ns Skew(Inter-Pair) < 0.20 * T(Pixel)[4][5] = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil Chrontel suggests matching between any two pairs be within 100mil.[5] => Δl < 100mil => Δt < Δl / v = 2540um / (150um/ps) = 17ps
Of these design parameters Chrontel's 100mil recommendation seems to be the most restrictive, but still not out of the realm of possibility and probably a good precautionary limit. With only 17ps of inter-pair skew we meet even much tighter skew timings. Having non-vanishing inter-pair skew seems to actually be beneficial for reducing Electro-Magnetic Interference (EMI) by avoiding simultaneous transitions on multiple lines. Indeed the standard seems to be designed to recover up to 5 bits of worst-case inter-pair skew.[6] (Half of the 10-bit pixel time.) A Texas Instruments (TI) employee specifically suggested to keep the clock pair longer than the data pairs.[7]
Intra-pair skew: (Requirements for HDMI v1.4) Toradex: Δt < 5ps[3] => Δl < v * Δt = 0.75mm ~= 30 mil Chrontel, Texas Instruments: T(bit) = 0.1 * T(Pixel) = 294ps Skew(Intra-Pair) = 0.15 * T(bit)[4][5] = 44.1ps => Δl = v * Δt = 6.62mm ~= 261 mil (Chrontel suggests, without saying why, that matching between signals should be within 5mil.[5] Given the context and calculations above suggesting 261 mil for total, this should probably be 5mil skew per segment.)
Intra-pair skew causes EMI.[8] One way to see this is to consider what we're trying to do by routing the differential signal on a differential pair of traces. The goal is to make the distance between the traces as small as possible and still maintain the differential impedance needed to match the rest of the transmission line. This reduces the size of the effective antenna. When the signals are propagating in parallel down this pair of traces the length of the effective dipole antenna is the distance between the two wavefronts. If the traces are parallel and equidistant from the source, the combined wavefront will be perpendicular to the traces and of minimal effective size. If a difference in distance from the source occurs between the traces, the combined wavefront will no longer be perpendicular to the traces and the effective size will be larger.
Toradex' "Layout Design Guide" has a great treatment of problems and suggested solutions throughout section 6 "High-Speed Layout Considerations". Of particular interest here is section 6.7 "Length Matching", pp. 21-25. Section 6.8 "Signal Return Path", pp. 25-29, is of considerable related interest.
Chamferred Corners (or Trace Bend Geometry)
I'm glad to see you are already using 45 degree bends instead of 90 degree corners. This helps the corners maintain the proper impedance. When serpentine traces (meanders) are needed to attain certain lengths of a single-ended trace, make sure individual segment lengths are at least 1.5x the width of the trace. Also, the spacing between parallel segments of the same trace should be at least 4x the width of the trace.[9]
Length Matching
Differential pair signals should not propagate asynchronously over a distance greater than 15mm[10] = 590mil. Thus the compensation for length mis-matches should be placed as close to the mismatch as possible. Differential traces can be segmented by a connector, pad (component or IC), or via.[10][5] "Each segment of a differential pair connection needs to be matched individually."[10]
Ideal serpentine trace geometry for equalizing differential traces consists of the following proportions: the spacing between traces in the meanders should not exceed twice the normal spacing, and the length of more widely spaced traces should not exceed three times the normal trace width.[10, see Figure 23]
References: [3] Toradex, page 38 [4] TI, page 4 [5] Chrontel, page 5 [6] https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-... [7] https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205 [8] https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_fo... [9] Toradex, page 17, Figures 12 & 13 [10] Toradex, pages 22-23
Bibliography: http://www.chrontel.com/media/Application%20Notes/AN-B026%20Rev0.2.pdf http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/... http://docs.toradex.com/102492-layout-design-guide.pdf
ok reading in full, cutting extraneous, answering only with confirmation.
On Tue, Aug 1, 2017 at 10:57 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So, while we will try to match the impedance of our traces (transmission lines) as carefully as possible to the characteristic impedance specified for the cable, until we get to 4.3 inches from the signal source the line driver should be able to squash most reflections on the leading edges (first quarter wavelength).
actual distance is 55mm, under half the 4.3in.
Inter-pair skew: (Requirements for HDMI v1.4) clock-data skew: Δt <150ps[3] => Δl < v * Δt = 22mm ~= 870mil T(Pixel) = 1/(pixel clock) = 2.94ns Skew(Inter-Pair) < 0.20 * T(Pixel)[4][5] = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil Chrontel suggests matching between any two pairs be within 100mil.[5] => Δl < 100mil => Δt < Δl / v = 2540um / (150um/ps) = 17ps
actual difference between CK and Tx2 is 55 - 48mm, or 7mm. so... 275 mil. whoops.
between CK and Tx2 is 55 - 52 = 3mm, so... 118 mil. again whoops.
Of these design parameters Chrontel's 100mil recommendation seems to be the most restrictive, but still not out of the realm of possibility and probably a good precautionary limit. With only 17ps of inter-pair skew we meet even much tighter skew timings. Having non-vanishing inter-pair skew seems to actually be beneficial for reducing Electro-Magnetic Interference (EMI) by avoiding simultaneous transitions on multiple lines. Indeed the standard seems to be designed to recover up to 5 bits of worst-case inter-pair skew.[6] (Half of the 10-bit pixel time.) A Texas Instruments (TI) employee specifically suggested to keep the clock pair longer than the data pairs.[7]
sounds like a good idea... and has to happen anyway: the clock lines have slightly further to go.
Intra-pair skew: (Requirements for HDMI v1.4) Toradex: Δt < 5ps[3] => Δl < v * Δt = 0.75mm ~= 30 mil Chrontel, Texas Instruments: T(bit) = 0.1 * T(Pixel) = 294ps Skew(Intra-Pair) = 0.15 * T(bit)[4][5] = 44.1ps => Δl = v * Δt = 6.62mm ~= 261 mil (Chrontel suggests, without saying why, that matching between signals should be within 5mil.[5] Given the context and calculations above suggesting 261 mil for total, this should probably be 5mil skew per segment.)
i try to meet that - 5 didn't know it was as little as 5mil though. that's absolutely tiny!
Chamferred Corners (or Trace Bend Geometry)
I'm glad to see you are already using 45 degree bends instead of 90 degree corners. This helps the corners maintain the proper impedance. When serpentine traces (meanders) are needed to attain certain lengths of a single-ended trace, make sure individual segment lengths are at least 1.5x the width of the trace. Also, the spacing between parallel segments of the same trace should be at least 4x the width of the trace.[9]
that's going to be very very hard to achieve: there is an extremely limited amount of space.
Length Matching
Differential pair signals should not propagate asynchronously over a distance greater than 15mm[10] = 590mil. Thus the compensation for length mis-matches should be placed as close to the mismatch as possible. Differential traces can be segmented by a connector, pad (component or IC), or via.[10][5] "Each segment of a differential pair connection needs to be matched individually."[10]
yeah i saw that in the toradex recommendations, otherwise there's skew between traces.
Ideal serpentine trace geometry for equalizing differential traces consists of the following proportions: the spacing between traces in the meanders should not exceed twice the normal spacing, and the length of more widely spaced traces should not exceed three times the normal trace width.[10, see Figure 23]
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
so thank you - much to correct and think about. really appreciated you finding all this stuff richard.
l.
2017-08-01 12:29 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
ok reading in full, cutting extraneous, answering only with confirmation.
On Tue, Aug 1, 2017 at 10:57 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So, while we will try to match the impedance of our traces (transmission lines) as carefully as possible to the characteristic impedance specified for the cable, until we get to 4.3 inches from the signal source the line driver should be able to squash most reflections on the leading edges (first quarter wavelength).
actual distance is 55mm, under half the 4.3in.
Inter-pair skew: (Requirements for HDMI v1.4) clock-data skew: Δt <150ps[3] => Δl < v * Δt = 22mm ~= 870mil T(Pixel) = 1/(pixel clock) = 2.94ns Skew(Inter-Pair) < 0.20 * T(Pixel)[4][5] = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil Chrontel suggests matching between any two pairs be within 100mil.[5] => Δl < 100mil => Δt < Δl / v = 2540um / (150um/ps) = 17ps
actual difference between CK and Tx2 is 55 - 48mm, or 7mm. so... 275 mil. whoops.
between CK and Tx2 is 55 - 52 = 3mm, so... 118 mil. again whoops.
Of these design parameters Chrontel's 100mil recommendation seems to be the most restrictive, but still not out of the realm of possibility and probably a good precautionary limit. With only 17ps of inter-pair skew we meet even much tighter skew timings. Having non-vanishing inter-pair skew seems to actually be beneficial for reducing Electro-Magnetic Interference (EMI) by avoiding simultaneous transitions on multiple lines. Indeed the standard seems to be designed to recover up to 5 bits of worst-case inter-pair skew.[6] (Half of the 10-bit pixel time.) A Texas Instruments (TI) employee specifically suggested to keep the clock pair longer than the data pairs.[7]
sounds like a good idea... and has to happen anyway: the clock lines have slightly further to go.
Intra-pair skew: (Requirements for HDMI v1.4) Toradex: Δt < 5ps[3] => Δl < v * Δt = 0.75mm ~= 30 mil Chrontel, Texas Instruments: T(bit) = 0.1 * T(Pixel) = 294ps Skew(Intra-Pair) = 0.15 * T(bit)[4][5] = 44.1ps => Δl = v * Δt = 6.62mm ~= 261 mil (Chrontel suggests, without saying why, that matching between signals should be within 5mil.[5] Given the context and calculations above suggesting 261 mil for total, this should probably be 5mil skew per segment.)
i try to meet that - 5 didn't know it was as little as 5mil though. that's absolutely tiny!
Chamferred Corners (or Trace Bend Geometry)
I'm glad to see you are already using 45 degree bends instead of 90 degree corners. This helps the corners maintain the proper impedance. When serpentine traces (meanders) are needed to attain certain lengths of a single-ended trace, make sure individual segment lengths are at least 1.5x the width of the trace. Also, the spacing between parallel segments of the same trace should be at least 4x the width of the trace.[9]
that's going to be very very hard to achieve: there is an extremely limited amount of space.
Length Matching
Differential pair signals should not propagate asynchronously over a distance greater than 15mm[10] = 590mil. Thus the compensation for length mis-matches should be placed as close to the mismatch as possible. Differential traces can be segmented by a connector, pad (component or IC), or via.[10][5] "Each segment of a differential pair connection needs to be matched individually."[10]
yeah i saw that in the toradex recommendations, otherwise there's skew between traces.
Ideal serpentine trace geometry for equalizing differential traces consists of the following proportions: the spacing between traces in the meanders should not exceed twice the normal spacing, and the length of more widely spaced traces should not exceed three times the normal trace width.[10, see Figure 23]
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
Between via's the length should be matched right? Length mismatch should be solved as soon as possible to accommodate eddy-currents right?
Found a nice post from TI https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
so thank you - much to correct and think about. really appreciated you finding all this stuff richard.
l.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
On Tue, Aug 1, 2017 at 2:51 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
[trimming a huge amount of unnecessary context on your behalf, mike... hint, hint....]
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
Between via's the length should be matched right? Length mismatch should be solved as soon as possible to accommodate eddy-currents right?
yes. the toradex article explains it very well, also mentions the importance of symmetry (as does the TI post).
Found a nice post from TI https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
nice! dang, above 10ghz the thickness of the via starts to matter and needs to be drilled out, post-production. dang.
*sigh* unfortunately symmetry is not completely achievable with the drastically-reduced amount of space available. the HDMI signals come out right at the bottom of the board.
l.
so thank you - much to correct and think about. really appreciated you finding all this stuff richard.
l.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
2017-08-01 16:11 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Tue, Aug 1, 2017 at 2:51 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
[trimming a huge amount of unnecessary context on your behalf, mike... hint, hint....]
My apologies to all.
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
Between via's the length should be matched right? Length mismatch should be solved as soon as possible to accommodate eddy-currents right?
yes. the toradex article explains it very well, also mentions the importance of symmetry (as does the TI post).
Found a nice post from TI https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
nice! dang, above 10ghz the thickness of the via starts to matter and needs to be drilled out, post-production. dang.
*sigh* unfortunately symmetry is not completely achievable with the drastically-reduced amount of space available. the HDMI signals come out right at the bottom of the board.
That might not be to problematic. I've search to the net for talk about running tracks on top of each other. It keeps hunting me. And found a knowledable awnser.
http://www.sigcon.com/Pubs/news/2_30.htm
On of the things mentioned is that the differential signals might not be quite aligned to begin with. So achieving symmetry might look nice on but can only give limited help in minimizing emission and pickup.
l.
On Tue, Aug 1, 2017 at 8:25 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-01 16:11 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
*sigh* unfortunately symmetry is not completely achievable with the drastically-reduced amount of space available. the HDMI signals come out right at the bottom of the board.
That might not be to problematic. I've search to the net for talk about running tracks on top of each other. It keeps hunting me. And found a knowledable awnser.
Thanks for the interesting read. It is an intriguing geometry and looks like it uses vertical space more than horizontal. I suppose we could make use of a 2-D EM field solver to figure out design parameters such as trace width, which layers to use (how much dielectric thickness between traces), and horizontal offset from other traces.
On of the things mentioned is that the differential signals might not be quite aligned to begin with. So achieving symmetry might look nice on but can only give limited help in minimizing emission and pickup.
I guess to get better than that we would have to characterize the differential signal sources and, if they have a repeatable output skew, then design the traces with that initial skew from the source. I have a suspicion that the important goals for this project include: 1. operational HDMI v1.4 interface supporting all operating modes of which the A20 chip is capable (clock up to 340MHz, data up to 3.4GHz) 2. EMI radiation below regulatory limits for all concerned agencies: FCC, CSA, EU, etc. 3. EMI sensitivity small enough to avoid disrupting proper operation of all systems of the EOMA68-A20.
Hopefully the drivers on the chip are aligned well enough to fit into the skew budget for HDMI operation and we are able to execute a PCB trace geometry to support all three goals. (I'm willing to bet on it!)
On Tue, Aug 1, 2017 at 8:11 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Aug 1, 2017 at 2:51 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Found a nice post from TI https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
nice! dang, above 10ghz the thickness of the via starts to matter and needs to be drilled out, post-production. dang.
Since we're not trying to support HDMI post v1.4 we don't have signals above 10GHz on this interface at least. Thankfully none of the signal trace vias need to be drilled out since our signals always traverse the whole via.
*sigh* unfortunately symmetry is not completely achievable with the drastically-reduced amount of space available. the HDMI signals come out right at the bottom of the board.
Hopefully most of what we can't accomplish with symmetry we can remedy with creativity.
On Tue, Aug 1, 2017 at 7:51 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-01 12:29 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
Between via's the length should be matched right? Length mismatch should be solved as soon as possible to accommodate eddy-currents right?
Correct on both counts.
Found a nice post from TI https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
Thanks for the link to an interesting article. Thankfully we are well below 10GHz on this interface and have 0 stub length as our signals traverse the via all the way from top to bottom or vice versa. We do have the option to specifically adjust the antipad or keepout sizes around our vias. More discussion of this topic in the upcoming section on impedance.
On Tue, Aug 1, 2017 at 4:29 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok reading in full, cutting extraneous, answering only with confirmation.
Great plan!
On Tue, Aug 1, 2017 at 10:57 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
[...] until we get to 4.3 inches from the signal source the line driver should be able to squash most reflections on the leading edges (first quarter wavelength).
actual distance is 55mm, under half the 4.3in.
I figured this wasn't going to be a problem and so I mentioned it to ease the tenor of the discussion.
Inter-pair skew: (Requirements for HDMI v1.4) clock-data skew: Δt <150ps[3] => Δl < v * Δt = 22mm ~= 870mil T(Pixel) = 1/(pixel clock) = 2.94ns Skew(Inter-Pair) < 0.20 * T(Pixel)[4][5] = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil Chrontel suggests matching between any two pairs be within 100mil.[5] => Δl < 100mil => Δt < Δl / v = 2540um / (150um/ps) = 17ps
actual difference between CK and Tx2 is 55 - 48mm, or 7mm. so... 275 mil. whoops.
between CK and Tx2 is 55 - 52 = 3mm, so... 118 mil. again whoops.
I wouldn't sweat too much breaking the 100mil target by hitting 275mil.
I didn't quite organize that very well. Here's what it should look like. Notice that requirements for the standard (HDMI v1.4, attested by both Chrontel and TI) are first and suggestions are specifically introduced with the verb, "suggests":
Inter-pair skew: (Requirements for HDMI v1.4) Chrontel, TI: T(Pixel) = 1/(pixel clock) = 2.94ns Skew(Inter-Pair) < 0.20 * T(Pixel)[4][5] = 588ps => Δl < v * Δt = 88.2mm ~= 3470mil Toradex suggests clock-data skew: Δt <150ps[3] => Δl < v * Δt = 22mm ~= 870mil Chrontel suggests matching between any two pairs be within 100mil.[5] => Δl < 100mil => Δt < Δl / v = 2540um / (150um/ps) = 17ps
Intra-pair skew: (Requirements for HDMI v1.4) Chrontel, TI: T(bit) = 0.1 * T(Pixel) = 294ps Skew(Intra-Pair) = 0.15 * T(bit)[4][5] = 44.1ps => Δl = v * Δt = 6.62mm ~= 261 mil Toradex suggests: Δt < 5ps[3] => Δl < v * Δt = 0.75mm ~= 30 mil (Chrontel suggests, without saying why, that matching between signals should be within 5mil.[5] Given the context and calculations above suggesting 261 mil for total, this should probably be 5mil skew per segment.)
A Texas Instruments (TI) employee specifically suggested to keep the clock pair longer than the data pairs.[7]
sounds like a good idea... and has to happen anyway: the clock lines have slightly further to go.
Happy coincidence!
Intra-pair skew: (Requirements for HDMI v1.4)
[...]
(Chrontel suggests, without saying why, that matching betweensignals should be within 5mil.[5] Given the context and calculations above suggesting 261 mil for total, this should probably be 5mil skew per segment.)
i try to meet that - 5 didn't know it was as little as 5mil though. that's absolutely tiny!
I'm going to guess that is probably due to the geometry of the differential traces where if the spacing is 5mil then a 5mil intra-pair skew lengthens the wavefront by sqrt(2) and it is now turned 45 degrees from the intended direction of propagation.
Chamferred Corners (or Trace Bend Geometry)
I'm glad to see you are already using 45 degree bends instead of 90 degree corners. This helps the corners maintain the proper impedance. When serpentine traces (meanders) are needed to attain certain lengths of a single-ended trace, make sure individual segment lengths are at least 1.5x the width of the trace. Also, the spacing between parallel segments of the same trace should be at least 4x the width of the trace.[9]
that's going to be very very hard to achieve: there is an extremely limited amount of space.
This section is mostly here to talk about the 45 degree versus 90 degree bends which is important for any high-frequency trace, be it single-ended or differential. The last part about proportions for meanders concerns single-ended traces (like if you needed it for CEC or some other *non-differential* signal). The proportions for differential meanders are down in the next section.
Length Matching
Differential pair signals should not propagate asynchronously over a distance greater than 15mm[10] = 590mil. Thus the compensation for length mis-matches should be placed as close to the mismatch as possible. Differential traces can be segmented by a connector, pad (component or IC), or via.[10][5] "Each segment of a differential pair connection needs to be matched individually."[10]
yeah i saw that in the toradex recommendations, otherwise there's skew between traces.
Ideal serpentine trace geometry for equalizing differential traces consists of the following proportions: the spacing between traces in the meanders should not exceed twice the normal spacing, and the length of more widely spaced traces should not exceed three times the normal trace width.[10, see Figure 23]
there's a lot of other stuff in here which is really good, such as making sure that lengths on each *layer* are matched, and that even when turning corners the lengths are matched. and matching just after VIAs *not* before... damn
I'm glad you're seeing good things. Matching should happen on the same side of the via (same segment) as the skew happens.
so thank you - much to correct and think about. really appreciated you finding all this stuff richard.
I wanted to present the parameters and principles so that you can make more well-informed choices. You don't have errors to correct but better information on which to base your choices.
arm-netbook@lists.phcomp.co.uk
-
Luke Kenneth Casson Leighton -
mike.valk＠gmail.com -
Richard Wilbur