On Sat, Aug 22, 2015 at 10:27 PM, Ralf-Peter Rohbeck via arm-netbook arm-netbook@lists.phcomp.co.uk wrote:

You could use two transistors in a darlington configuration

just reading about that here: http://www.electronics-tutorials.ws/blog/relay-switch-circuit.html

or add a diode and a resistor to the base of the transistor. Either would cause an effective 1.4V VBE needed to turn the transistor on. OTOH with a Germanium or Schottky diode you should be OK as long as EXT_BOOT0 is a CMOS output because it'll go to almost 0V if the current is low. Not sure what the levels might be. Even a nominally TTL output should go much lower than 0.7V at low current.

ralf, really appreciate the response. any chance you could find a random image on the internet as a demo circuit, or perhaps draw it out for me?

at the moment i'm considering using a 2nd transistor, powered from the other board (yes it'll be TTL - just with a different voltage).

basically this design is split into two boards, one is the EOMA68 main PCB with the CPU Card: i'd like the CPU Card to control the boot process (for firmware re-flashing) of the STM32F072, which is on the 2nd PCB.

but, if the PCB is disconnected for any reason (testing purposes) i'd like it to operate "stand-alone", powering up in "normal operation", which requires that BOOT0 be connected to GND with e.g. a 10k resistor.

the different TTL voltages that the CPU card(s) can operate at is what's the key issue, and, also, i don't want to put in another pin to send over the TTL REF voltage over to the STM32F072 board (unless absolutely necessary).

what i'm currently thinking is, put one transistor on the one PCB and another one one the other. in effect a "buffer" circuit.

mmmm.... also.... just checking the datasheet (DM00090510 section 6.3.14) it says that BOOT0's threshold level is "0.3 * (VIN) - 0.3". that works out at 0.69 volts, so anything with a standard 0.7v diode... wark-wark :)

ARGH you know what? i'm just going to say if normal operation is needed in stand-alone, put a jumper across EXT_BOOT0 :)

i'll redo the circuits in a mo....

l.

On Sunday 23 August 2015 15:52:27 Luke Kenneth Casson Leighton wrote:

http://hands.com/~lkcl/ttl_logic_circuit2.png

still don't feel completely happy (esp. with the schottky diode), i feel another transistor might be needed especially because VREFTTL (for the EOMA68_BOOT0 TTL level) could be *lower* than 3.3v.

There's no resistor to limit the current when ext_boot0 is up (from ext_boot0 to gnd).

But the schottky diode will prevent any current to go there... I don't see how the first transistor can be switched on...

On Sunday 23 August 2015 20:14:18 Dominique Dumont wrote:

When the input is 0, the transistor emitter is driven to ~ 0.3V which should switch off the transistor.

Even better, the emitter can be driven to 0 V bby putting the 100k resistor before the 10k. (attached png)

Hope this helps

ralf, dominique, phil: i believe this is what i'm looking for, let me try and work through it, see if i got it right:

http://upload.wikimedia.org/wikipedia/commons/thumb/8/81/TTL_NOT_gate.svg/50...

except, the 1st transistor will be supplied by VREFTTL (from the CPU) and the 2nd is supplied by VCC-3V3 (from the STM32F).

the 1st transistor is against the flow of current in the instance where VREFTTL is less than VCC-3V3.

when the input is at 0V:

* 1st transistor goes "on", so current flows through the 1st resistor (at VREFTTL). however the collector sits at 0.7v. * the implications of that for the 2nd transistor is: it can't switch on. * therefore, the 2nd transistor, being "off", has its own resistor up at VCC-3V3.

when the input is at VREFTTL (or close to it):

* 1st transistor is "off", *BUT* is acting as a diode from base to collector. * this results in (VREFTTL-0.7v) going into the 2nd transistor's base * that makes the 2nd transistor switch ON * that results in current flow across the 2nd transistor * that makes the saturation voltage from collector to emitter 0.3v which is what's needed to have BOOT0 at CMOS logic level "0".

anyone see any flaws?

l.

On Monday 24 August 2015 14:19:49 Luke Kenneth Casson Leighton wrote:

anyone see any flaws?

It should work.

But I don't see why the first transistor is needed. Well, it's only a few cents...

All the best

Yes that's what I'd use. You'll still need a 100k pull-up from EXT_BOOT0 to VCC to keep the transistors on when EXT_BOOT0 is disconnected or high. You don't need the high beta of the combined transistors, just the increased VBE, so you could replace Q1 with a silicon diode with the anode on EXT_BOOT0 and the cathode on B of Q3.

On 08/23/2015 07:52 AM, Luke Kenneth Casson Leighton wrote:

ok so i redid it, using a darlington pair, because yes the voltage definitely needs to be below 0.69v at the output: also, forget about the "disconnected" operation, that can be done with a jumper.

http://hands.com/~lkcl/ttl_logic_circuit2.png

still don't feel completely happy (esp. with the schottky diode), i feel another transistor might be needed especially because VREFTTL (for the EOMA68_BOOT0 TTL level) could be *lower* than 3.3v.

l.

On Tue, Aug 25, 2015 at 12:31 AM, Daniel Serpell daniel.serpell@gmail.com wrote:

Hi!

On Sat, Aug 22, 2015 at 2:21 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:

...

hi folks could someone please help analyse this circuit to see if it is correct?

http://hands.com/~lkcl/ttl_logic_circuit.png

the requirement:

• an STM32F's "BOOT0" is, by default "pulled to GND" in order that

"normal" operation happens

• the boot operation needs to be selectable by a GPIO from a main CPU

(TTL, with a different voltage)

• if however the main CPU's GPIO is *DISCONNECTED*, "normal" operation

of the STM32F is required.

so, the main things here are:

• the STM32F is run from a 3.3v supply

• the CPU can be a totally different TTL voltage level from the

STM32F. it could be 5.0V, it could be 3.3v, it could be 3.0v, it could be even 1.8v.

• the default behaviour needs to be "pull to GND", even if the input

is floating.

A little late to the discussion, but I would use something like: https://github.com/sparkfun/Logic_Level_Bidirectional

The schematic is here: https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional...

To assure that the output is low when the LV input is disconnected, you could add a resistance from the input to ground, I would use a 2k resistor, so that at 1.8V the gate has 1.5V, setting a low state in the output.

This circuit is cheap, and you would use only 3 resistors and one FET.

ta daniel, yes i saw this circuit around in the exploration i've been doing.

the only problem i have with it is this:

when the input is at 0V, i assume that means that the other side of the MOSFET also goes to 0V (plus a little bit - say 0.1V).

however if the input were to go to, say.... 0.6V (because that's within TTL levels), then the output would *also* go to 0.6V, plus a little bit, that's 0.7v.

.... and it's *way* over the acceptable threshold for BOOT0, which is a full 0.3 volts *lower* than CMOS. in this case (with a 3.3v supply) it's 3.3 * 0.3 - 0.3 which is 0.69v...

that's *barely* within tolerance.

so i feel that some additional transistor or other components are needed when using the MOSFET in order to make sure that the input is definitely definitely pulled right down.

i may be wrong here, please do tell me if i am.

ralf wrote:

You don't need the high beta of the combined transistors,

i'm not sure what high beta is, but the output definitely needs to go below 0.69 volts in order to trigger BOOT0 ROM mode. would the suggested circuit (with the silicon diode) do that?

thanks all,

l.

On Tue, Aug 25, 2015 at 4:18 AM, Daniel Serpell daniel.serpell@gmail.com wrote:

Hi!,

On Mon, Aug 24, 2015 at 9:45 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:

...

On Tue, Aug 25, 2015 at 12:31 AM, Daniel Serpell daniel.serpell@gmail.com wrote:

...

The schematic is here: https://cdn.sparkfun.com/datasheets/BreakoutBoards/Logic_Level_Bidirectional...

To assure that the output is low when the LV input is disconnected, you could add a resistance from the input to ground, I would use a 2k resistor, so that at 1.8V the gate has 1.5V, setting a low state in the output.

This circuit is cheap, and you would use only 3 resistors and one FET.

ta daniel, yes i saw this circuit around in the exploration i've been doing.

the only problem i have with it is this:

when the input is at 0V, i assume that means that the other side of the MOSFET also goes to 0V (plus a little bit - say 0.1V).

however if the input were to go to, say.... 0.6V (because that's within TTL levels), then the output would *also* go to 0.6V, plus a little bit, that's 0.7v.

No, it will be higher, because in that case the MOSFET would turn off a little more and it's resistance would go up (1.8V at LV minus 0.6V = 1.2V at gate).

ok. so.... if the input was at 0V the output would go to... what? if it's above 0.69v, then that level-shifting circuit can't be used as-is. BOOT0 simply wouldn't be enabled: it requires below 0.69v when the STM32F072 is operated at 3.3v.

But I don't understand why you are talking about "TTL" levels here, as:

1. I could not think on any way that an old TTL output device would be

connected to that input. 2) TTL devices had about 0.2V output, with relatively high current output.

i needed a specification for EOMA68, so i picked one. TTL seemed like a good idea. we're still in "development" phase so an alternative could be picked... i don't mind changing it to e.g. CMOS now that there's a VREFTTL.

In fact, the problem with TTL devices was that the HIGH output had low current capability, so you need to assure that the HIGH input threshold was low enough to allow for the low driving currents.

hmmm ok. so putting CMOS as the specification would be better.

In your case, you need the input to toggle on a variable voltaje digital output, (1.8V or 2.5V or 3.3V),

.... which needs to be specified, then every possible combination verified...

unfortunately this isn't like a "normal" electronics single-board design ( make a decision, pick a CPU, pick an EC, test a couple of voltages and then forget about it).

it's a bit of a risk developing with only one threshold voltage (most of the SoCs i've used have been 3.3v) but all the circuits need to cater for variable future VREFTTL.

whatever is picked, though, this particular circuit has an added wrinkle. even if CMOS is picked as the EOMA68 GPIO specification, it cannot be assumed that the low voltage *will* be reached, it has to be assumed worst-case i.e. that the low voltage will be 0.3*VREFTTL (which in the case of 3.3v will be 0.99v).

BOOT0 has that *different* low threshold from the rest of the [CMOS] STM32F072 GPIO pins: the formula is 3.3 * 0.3 - 0.3.

so whatever circuit is used, it *must* output a voltage *below* 0.69v even when its input is between 0 and 0.99v... when VREFTTL is 3.3v.

i think... i have one pin spare: i think it might be a good idea to send over VREFTTL to the board and look at a unidirectional level shifter IC.

l.