By the way, what is the status of the microdesktop design v1.7? Have you already invested in parts (specifically the 2x10 header) and/or circuit boards?
On Tue, Jul 3, 2018 at 1:57 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
By the way, what is the status of the microdesktop design v1.7? Have you already invested in parts (specifically the 2x10 header) and/or circuit boards?
yep all good. the funds that were transferred to mike 18+ months ago ($60k) are down to around $45k now and he's got most of that left with which to order components for the 1.7 md and 2.7.5 card.
l.
On Jul 3, 2018, at 03:19, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Jul 3, 2018 at 1:57 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
By the way, what is the status of the microdesktop design v1.7? Have you already invested in parts (specifically the 2x10 header) and/or circuit boards?
yep all good. the funds that were transferred to mike 18+ months ago ($60k) are down to around $45k now and he's got most of that left with which to order components for the 1.7 md and 2.7.5 card.
I was asking with regard to the possibility of releasing a microdesktop v1.8 with a few refinements (presumably electrical/electronic changes that fit within the same form factor, id est, no change to the case).
Why? 1. Open up more possibilities for experimentation by tripling the number of GPIO lines available at expansion connector(2 → 6). 2. Add soft-start to the power regulator for 3.3V supply. 3. Support VESA DDC Plug and Play monitor detection regardless of power-up order between monitor and computer.[1] 4. Improve signal quality (and reduce radiated/coupled EMI) for VGA interface. 5. Improve Electro-Static Discharge protection (page 1 of the schematic says: “TODO: ESD protection”).
How? 1. Bring the remaining 4 GPIO lines from the EOMA68 connector (J14 pins 20,54,21,55) to the expansion header(J5). Dropping VESA_SCL and VESA_SDA lines from J5 (available and used on VGA connector J4) gets us two pins for free. Then we either get a larger connector (2x11 instead of 2x10), find two other signals to drop from the expansion header (EOMA68-I2C_SCL, EOMA68-I2C_SDA which are connected to the serial EEPROM for chassis identification?), or decide we are happy to have doubled the GPIO presence (2 → 4) and stop. 2. Add a 10K Ohm resistor between +5V and Enable(pin 1) on U9. 3. Add another SY6280 current limiter for +5V and connect to VGA pin 9 (VESA power). Seems to be some difference of opinion on current requirements: 50mA[2], 300mA-1000mA[1]. If we were to limit at 300mA, it should easily supply the needs of I2C serial EEPROM and probably not over-tax our power supply. 4. Route signals as high-speed/frequency pairs.[1] A. Change the name of VGA pins(J4): pin Name 5 HSYNC_RTN 6 RED_RTN 7 GREEN_RTN 8 BLUE_RTN 9 PWR 10 VSYNC_DDC_RTN B. Make sure the following pairs are routed as microstrip pairs from connector pins to signal driver: VGA_ROUT/VGA_R(1), RED_RTN(6) VGA_GOUT/VGA_G(2), GREEN_RTN(7) VGA_BOUT/VGA_B(3), BLUE_RTN(8) VGAHSYNC/VGA_HSYNC(13), HSYNC_RTN(5) VGAVSYNC/VGA_VSYNC(14), VSYNC_DDC_RTN(10)
Return lines should connect to ground pins of signal driver and/or ground side of power supply decoupling capacitor at signal driver. The first three pairs (video lines) should be over unbroken ground plane as they are the highest-frequency lines (12.6MHz-388MHz depending on video mode).
Add VREFTTL decoupling capacitor next to R12 and R8 (pull-ups for VESA_SCL and VESA_SDA) then route the following pairs from VGA connector to pull-ups/decoupling capacitor ground: VESA_SDA/SDA(12), VSYNC_DDC_RTN(10) VESA_SCL/SCL(15), VSYNC_DDC_RTN(10)
5. Filter VGA cable shield connection to ground with ferrite beads (J4 pins 16,17). Likewise USB2 ports (J11, J3) pins M0 and M1. Also EOMA68 connector (J14) pins “0”, “0/2”, if those are connector shield connections? What are J14 pins 73 and 74? (They are labelled “GND” but left unconnected?)
We don't have a metal chassis here to connect the shields directly to. If we did, I'd suggest connecting shields to chassis ground and then ferrite bead to separate chassis ground from power/signal ground.
For VESA_SDA and VESA_SCL, add diode limiters connected to ground similar to ESD117-ESD123 on the SD bus lines provided the diode-limiting voltage is greater than VREFTTL nominal range. Otherwise use BAT54S connected between ground and VREFTTL.
Add BAT54S connected between ground and USB2VBUS across USB2 data lines EOMA68-DM0, EOMA68-DP0, DM2, DP2.
Just some thoughts. ;>)
Richard
References: [1] https://en.wikipedia.org/wiki/VGA_connector [2] https://en.wikipedia.org/wiki/Display_Data_Channel
Some thoughts:
- Add another SY6280 current limiter for +5V and connect to VGA pin
9 (VESA power). Seems to be some difference of opinion on current requirements: 50mA[2], 300mA-1000mA[1]. If we were to limit at 300mA, it should easily supply the needs of I2C serial EEPROM and probably not over-tax our power supply.
I've also seen the VGA/HDMI +5V used to power various converters (most often, HDMI->VGA, but I imagine the inverse is sometimes used as well).
For VESA_SDA and VESA_SCL, add diode limiters connected to ground similar to ESD117-ESD123 on the SD bus lines provided the diode-limiting voltage is greater than VREFTTL nominal range. Otherwise use BAT54S connected between ground and VREFTTL.
Is it not possible that VESA_SDA and VESA_SCL are 5V? If so, they could require level shifting from 5V, am I wrong here?
Cheers! Arsenijs
On Tue, Jul 17, 2018 at 7:02 AM, Pičugins Arsenijs crimier@yandex.ru wrote:
Some thoughts:
- Add another SY6280 current limiter for +5V and connect to VGA pin
9 (VESA power). Seems to be some difference of opinion on current requirements: 50mA[2], 300mA-1000mA[1]. If we were to limit at 300mA, it should easily supply the needs of I2C serial EEPROM and probably not over-tax our power supply.
I've also seen the VGA/HDMI +5V used to power various converters (most often, HDMI->VGA, but I imagine the inverse is sometimes used as well).
I agree. I designed a converter that was powered by VGA DDC pin 9 power or, in the absence of that, the VESA DDC SDA and SCL pull-up, or the VGA horizontal and vertical synchronization signals. I don't remember exactly how much power it used but it was relatively efficient as I used low-power CMOS PAL (Programmable Array Logic, precursor to FPGA's). Basically its largest-current operating mode was driving to TTL loads across the video cable.
For VESA_SDA and VESA_SCL, add diode limiters connected to ground similar to ESD117-ESD123 on the SD bus lines provided the diode-limiting voltage is greater than VREFTTL nominal range. Otherwise use BAT54S connected between ground and VREFTTL.
Is it not possible that VESA_SDA and VESA_SCL are 5V? If so, they could require level shifting from 5V, am I wrong here?
It turns out VESA DDC uses I2C signalling.[1] I2C signalling is bi-directional open drain or open collector so the high state is due to a pull-up resistor. The I2C bus voltage can be +5 V or +3.3 V, although other voltages are permitted.[2] All the devices on the bus have to tolerate the bus voltage.
In my experience, the VESA DDC reference design used a pull-up supply of +5 V. The EOMA68 card doesn't have to drive it that high, simply go hi-Z and the pull-up resistor in the microdesktop will pull it that high. But the EOMA68 card will have to tolerate +5 V on those two lines (VESA_SDA, VESA_SCL) or we jump into the tricky area of logic-level translation for bi-directional open-drain signals.
Good observations. Thanks Arsenijs!
References: [1] https://en.wikipedia.org/wiki/Display_Data_Channel [2] https://en.wikipedia.org/wiki/I%C2%B2C
Addendum
Why? 1. Make VESA DDC lines conform to VESA DDC spec. (VDD=5.0V, I2C signalling)[1] 2. Respect VREFTTL in the range of 3.3-5.0V on EOMA side of VESA DDC lines. 3. Respect EOMA requirement that all lines except EOMA I2C be tri-stated at power on.
How? 1. Connect pull-up resistors for VESA_SDA(R8) and VESA_SCL(R12) to VESA_PWR (+5.0V) instead of VREFTTL. Maximum current requirement on VESA_PWR is ~670uA. 2. Implement circuit in attached diagram[EOMA_I2C_circuit_sketch_small.png] on each of SDA and SCL. I have attached a spreadsheet[EOMA_I2C_VESA_calc.pdf] showing how this accommodates the I2C signalling for VDD=3.3V=VREFTTL and VDD=5.0V.[2] It also accommodates the EOMA68 VREFTTL input levels by not allowing the EOMA side of the signal to exceed one Schottky diode drop(0.3V) above VDD=3.3V. 3. Enable the current limiting regulator (SY6280) for VESA_PWR (+5.0V on VGA pin 9) with latch of LCDDE when it first goes active (line coming from EOMA68 connector).
References:
[1] https://en.wikipedia.org/wiki/Display_Data_Channel [2] http://www.nxp.com/documents/user_manual/UM10204.pdf
Here's the circuit diagram-scribbled on a piece of paper with pencil. Photo shot with phone camera and cropped and scaled down in GIMP. If it needs to be larger to be readable, I still have the original so can rescale as needed.
i added it here http://rhombus-tech.net/community_ideas/micro_desktop/mdesktop_i2c.jpg
could you link that on the page http://rhombus-tech.net/community_ideas/micro_desktop/ --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Jul 18, 2018 at 1:52 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here's the circuit diagram-scribbled on a piece of paper with pencil. Photo shot with phone camera and cropped and scaled down in GIMP. If it needs to be larger to be readable, I still have the original so can rescale as needed.
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
On Jul 17, 2018, at 19:04, Pičugins Arsenijs crimier@yandex.ru wrote:
- Implement circuit in attached
diagram[EOMA_I2C_circuit_sketch_small.png] ...
Did not get your attachments. I'm thinking they were scrubbed by the ML software? Maybe post a link - imgur/other sharing service?
Arsenijs
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
On Tue, Jul 17, 2018 at 7:04 PM, Pičugins Arsenijs crimier@yandex.ru wrote:
- Implement circuit in attached
diagram[EOMA_I2C_circuit_sketch_small.png] ...
Did not get your attachments. I'm thinking they were scrubbed by the ML software? Maybe post a link - imgur/other sharing service?
It is likely the PDF was scrubbed. The PNG got into moderation because it was too large. So I sent them both to the E-mail address at the bottom of the mailing list signature, below:
arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
Here are links to the files: ftp://lists.phcomp.co.uk/files/arm-netbook/EOMA_I2C_VESA_calc.pdf
ftp://lists.phcomp.co.uk/files/arm-netbook/EOMA_I2C_circuit_small.png
These are evidently by default good till 18 August 2018. If they are still cogent to the discussion I will try to keep them around longer.
Richard
Richard can you please edit community_ideas micrideksoo oage rhuombustech maintain all of this there revisioons to revisions of email knoen to be not a sustainable way to track detailed important information
On Wednesday, July 18, 2018, Richard Wilbur richard.wilbur@gmail.com wrote:
Addendum
Why?
- Make VESA DDC lines conform to VESA DDC spec. (VDD=5.0V, I2C
signalling)[1] 2. Respect VREFTTL in the range of 3.3-5.0V on EOMA side of VESA DDC lines. 3. Respect EOMA requirement that all lines except EOMA I2C be tri-stated at power on.
How?
- Connect pull-up resistors for VESA_SDA(R8) and VESA_SCL(R12) to
VESA_PWR (+5.0V) instead of VREFTTL. Maximum current requirement on VESA_PWR is ~670uA. 2. Implement circuit in attached diagram[EOMA_I2C_circuit_sketch_small.png] on each of SDA and SCL. I have attached a spreadsheet[EOMA_I2C_VESA_calc.pdf] showing how this accommodates the I2C signalling for VDD=3.3V=VREFTTL and VDD=5.0V.[2] It also accommodates the EOMA68 VREFTTL input levels by not allowing the EOMA side of the signal to exceed one Schottky diode drop(0.3V) above VDD=3.3V. 3. Enable the current limiting regulator (SY6280) for VESA_PWR (+5.0V on VGA pin 9) with latch of LCDDE when it first goes active (line coming from EOMA68 connector).
References:
[1] https://en.wikipedia.org/wiki/Display_Data_Channel [2] http://www.nxp.com/documents/user_manual/UM10204.pdf _______________________________________________ arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netbook@files.phcomp.co.uk
On Tue, Jul 17, 2018 at 7:43 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Richard can you please edit community_ideas micrideksoo oage rhuombustech maintain all of this there revisioons to revisions of email knoen to be
not
a sustainable way to track detailed important information
Luke,
That's a great idea. I was just noticing how the updates weren't fitting into the original so well and thinking I didn't know which wiki page on which to write stuff.
Thank you for answering my question before I had a chance to ask it!
Richard
arm-netbook@lists.phcomp.co.uk
-
Luke Kenneth Casson Leighton -
Pičugins Arsenijs -
Richard Wilbur