The goal of the taper is to minimize the reflection coefficient involved with changes in impedance caused by changes in transmission line geometry. In essence we are trying to make the changes so gentle that we don't scare any electrons. The scared electrons reflect at the point of abrupt changes in impedance(flee back in the direction they came from) which weakens the signal delivered to the HDMI cable and, finally, the display. (Forgive the anthropomorphization of the electrons--it is purely for illustrative purposes.)
As the high-frequency differential lines traverse the board from processor pin to connector pin certain parts of the geometry and electromagnetic environment stay fairly constant, other aspects in certain places are not conducive to the transmission environment needed by the HDMI signals we wish to deliver to the connector.
Three principles are at work here: 1. Whatever conditions are apparent over the majority of the conduction path will dominate the transmission characteristics. (You could think of the overall impedance as being similar to a length-weighted average of the local impedance of all the sections along the path.) 2. The abruptness of changes in geometry will determine the abruptness of changes in impedance and thus the reflection coefficient associated with the perturbation. 3. Reflections are more troublesome the further you get from the signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver.
The trace width stays mostly constant at 5mil except for component pads at processor, ESD chip, and connector and the two through-hole vias used to transition from layer 1 (processor) to layer 6 (room for differential microstrip transmission lines) back to layer 1 (connector).
Both the signal trace copper thickness and the dielectric thickness between signal traces and ground plane change only at the signal vias.
The room available on layer 6 allows us to make a controlled-impedance differential transmission line for a good share of the transmission path. Since the HDMI standard specifies 100 +/-15% Ohm impedance, we have designed the geometry to provide a characteristic impedance close to the upper end of the tolerance of the nominal impedance. We have room to impose this geometry for most of the length of the sojourn. At both ends the space is restricted such that the close quarters will no doubt result in a lower local impedance.
Where we have room, the distance between a differential pair and any other copper (be it another differential pair or ground) is 15mil. At both ends this is restricted by the spacing between lands in the component layouts down to 5-7mil.
From the first principle, we see that the influence of the lower local impedance from the restricted sections will serve to lower the overall impedance. In order to stay within the tolerances of the nominal impedance we attempt to limit the length of the restricted sections (where the inter-pair distance <15mil). In some places this could lead us to maintain 15mil inter-pair distance right up to an obstruction which imposes a 5-7mil inter-pair distance. The second principle leads us to recognize this is an abrupt change and expect that it will cause reflections. The third principle suggests it is more important to deal with abrupt changes at the connector end of the transmission line than the processor end.
Hence, we are exploring the feasibility of tapering the inter-pair distance down from 15mil to 5mil as we get to the connector end, in order to soften the effects of the unavoidable space restrictions at the connector end. The other important point is that since we are dealing with differential signals, we are interested in trying to maintain symmetry in dealing with the two traces of each differential pair, lest we push signal energy into common-mode.
The idea was inspired by my reading of a discussion on "Microwaves101"[*] of an impedance taper first described by R. W. Klopfenstein in a paper titled "A Transmission Line Taper of Improved Design", published in the Proceedings of the IRE, page 31-35, January 1956.
We aren't really doing his work justice as our frequencies are so low that our board is too small to accommodate the length required to get the good low frequency response he demonstrates. Nevertheless, we are interested in making the sequence of small transitions in a somewhat similar fashion.
Transmission Line geometry (widths)
North ground fill keep out Inter-pair Distance = 15mil HDMI TX2P trace = 5mil Intra-pair Spacing = 5mil HDMI TX2N trace = 5mil Inter-pair Distance = 15mil HDMI TX1P trace = 5mil Intra-pair Spacing = 5mil HDMI TX1N trace = 5mil Inter-pair Distance = 15mil HDMI TX0P trace = 5mil Intra-pair Spacing = 5mil HDMI TX0N trace = 5mil Inter-pair Distance = 15mil HDMI TXCP trace = 5mil Intra-pair Spacing = 5mil HDMI TXCN trace = 5mil Inter-pair Distance = 15mil South ground fill keep out
Adding this up yields a total = 135mil
When we scale the Inter-pair Distance = 5mil, the total = 85mil
This drops 50mil in width.
<step> <Inter-pair Distance> <Change> 0 15mil 1 14mil -1mil 2 13mil -1mil 3 12mil -1mil 4 10mil -2mil 5 08mil -2mil 6 07mil -1mil 7 06mil -1mil 8 05mil -1mil
If we use 15mil along the signal conduction path from the onset of one change to the next and 45 degree turns to initiate and complete all the changes, and if we choose a geometry to lengthen TXC (clock) the most and leave unchanged TX2, the length along the signal path of the taper will be 7*15mil + 4*1mil = 109mil after which we have no need of manual keep outs for the ground fill as the board rule of 5mil minimum Cu-Cu spacing will suffice.
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
Diagram attached below.
Good grief that took awhile! I'm now completely sold on the concept of Computer-Aided Design (I've used some awkward implementations before but this was done with pencil, pen, measuring tape, and book spine for straight edge).
Reference: [*] https://www.microwaves101.com/encyclopedias/klopfenstein-taper
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On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
The goal of the taper is to minimize the reflection coefficient involved with changes in impedance caused by changes in transmission line geometry. In essence we are trying to make the changes so gentle that we don't scare any electrons. The scared electrons reflect at the point of abrupt changes in impedance(flee back in the direction they came from) which weakens the signal delivered to the HDMI cable and, finally, the display. (Forgive the anthropomorphization of the electrons--it is purely for illustrative purposes.)
i get it. and it's fun, too. reminds me of "B.O.B" from Monsters for some reason.
Dr Cockroach: "Look out, here comes..." Susan: *pause*... "Susan". B.O.B.: "SuuUuuusan... oo that does sound scarey. i scared myself"
btw i miiight be able to do a pair of arcs on each side of keepout area, in "S" format, where it needs to narrow / widen.
are you able to take a closer-up photo or a higher-res version, don't worry about the file limit to the list i'll "approve" it when i see it. the image is 320x240 and it's too blurry to make out the writing and notes. not too hi-res btw! :) some of these iphones... dang. what i do is: use GIMP, convert to JPEG, set it at "35% compression", that's a good compromise on quality and size, then you can get away with even as high as 1000x1000 @ only... 80-200k or so depending on complexity. i also tend to select "Image | Mode | Greyscale" on pencil-drawn pictures.
l.
photo: Small 29.3KB Medium 86.5KB Large 790KB Actual 1.8MB
I believe I selected the smallest option last time. I'll try "Medium" this time.
On Tue, Dec 5, 2017 at 4:28 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
photo: Small 29.3KB Medium 86.5KB Large 790KB Actual 1.8MB
I believe I selected the smallest option last time. I'll try "Medium" this time.
yehyeh too small - medium's great. make it just the one attachment, JPG only. or, y'know what? email me (directly) the actual image, i'll take care of it.
l.
On Tue, Dec 5, 2017 at 12:22 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Dec 5, 2017 at 4:28 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
photo: Small 29.3KB Medium 86.5KB Large 790KB Actual 1.8MB
I believe I selected the smallest option last time. I'll try "Medium" this time.
yehyeh too small - medium's great. make it just the one attachment, JPG only. or, y'know what? email me (directly) the actual image, i'll take care of it.
got it, richard. i got the original of the HTML-embedded message (i set up the list to strip HTML MIME-embedded attachments), but instead i received the *original* message.
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Reflections are more troublesome the further you get from the
signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver.
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
okaay so the idea is, just after the long straight you make a series of very tiny corrections by bringing each of the tracks inwards - closer together - so that when you get to the point where you *have* to be 5-7mil apart you're already neeearrrrly that far apart *anyway* so it's not so bad.
ok :) that's perfectly doable.
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On Tue, Dec 5, 2017 at 12:41 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Reflections are more troublesome the further you get from the
signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver.
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
okaay so the idea is, just after the long straight you make a series of very tiny corrections by bringing each of the tracks inwards - closer together - so that when you get to the point where you *have* to be 5-7mil apart you're already neeearrrrly that far apart *anyway* so it's not so bad.
ok :) that's perfectly doable.
so, a quick check: it's easier, due to the VIAs (i am *not* moving them!! certainly not the diff-pairs!) to keep TX1 exactly where it is, and move TX2, TX0 and TXC all inwards. i'll also move the last change from N to NE that goes round the GND via a bit closer in.
question: does it *really matter* that the tapering occurs after the 45 degree group turn or is it ok to simply... ok picture 1 or picture 2? :)
thoughts appreciated
On Dec 5, 2017, at 05:41, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
okaay so the idea is, just after the long straight you make a series of very tiny corrections by bringing each of the tracks inwards - closer together - so that when you get to the point where you *have* to be 5-7mil apart you're already neeearrrrly that far apart *anyway* so it's not so bad.
ok :) that's perfectly doable.
Sweet!
The reason for all the detail is to try and make the changes gradual enough to avoid causing big reflections from the taper itself but also make the geometry symmetric so we avoid turning differential signal into common mode.
Notice that all the tracks and keepouts start a move "in" towards TX2 once every 15mil and then stay at that distance for the remainder of that step. Notice also that all the tracks and keepouts move in except TX2 (since our goal is that it be the shortest--or moreso that TXC be the longest). At the 5mil-inter-pair-distance end of the taper the manual keepouts become superfluous in light of your 5mil minimum Cu-Cu spacing design rule which then simplifies the connector end of the layout.
I threw "step 0" in there to say let's allow things to at least settle a little after making the turn before we start into the taper.
Once we get into that tight bundle then we have to carefully pull the pairs off in order to avoid undoing all our work. I'll send another drawing later this afternoon. (I'm waiting for the dental hygienist, right now.)
The idea is to have the bundle running NE, then simultaneously turn the bottom (southernmost) pair due E while the rest of the bundle turns due N for at least 15mil before turning back NE. This makes a 90 degree corner between the bundle and the pair which is leaving and gives enough space to allow ground fill between immediately.
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On Tue, Dec 5, 2017 at 9:15 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The reason for all the detail is to try and make the changes gradual enough to avoid causing big reflections from the taper itself but also make the geometry symmetric so we avoid turning differential signal into common mode.
wait... so there's *multiple* of those tiny "wiggles" needed? what about... i know: what about doing some of those curves as double-S double-ended arcs, like in that 1965 paper you found? i'll draw it tomorrow
Notice that all the tracks and keepouts start a move "in" towards TX2 once every 15mil and then stay at that distance for the remainder of that step. Notice also that all the tracks and keepouts move in except TX2 (since our goal is that it be the shortest--or moreso that TXC be the longest).
1912 for TX2, 2075 for TX1, 2036 for TX0, 2225 for TXC.
noo problem about keeping TX2 the longest, even with a *lot* of taper-wiggling. keeping TX1 stable (see diagrams i sent) would not be a problem.
At the 5mil-inter-pair-distance end of the taper the manual keepouts become superfluous in light of your 5mil minimum Cu-Cu spacing design rule which then simplifies the connector end of the layout.
ok that's good
I threw "step 0" in there to say let's allow things to at least settle a little after making the turn before we start into the taper.
Once we get into that tight bundle then we have to carefully pull the pairs off in order to avoid undoing all our work. I'll send another drawing later this afternoon. (I'm waiting for the dental hygienist, right now.)
ok :)
The idea is to have the bundle running NE, then simultaneously turn the bottom (southernmost) pair due E while the rest of the bundle turns due N for at least 15mil before turning back NE. This makes a 90 degree corner between the bundle and the pair which is leaving and gives enough space to allow ground fill between immediately.
drawing. even a rough sketch. needed definitely
2017-12-05 13:41 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Reflections are more troublesome the further you get from the
signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver.
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
okaay so the idea is, just after the long straight you make a series of very tiny corrections by bringing each of the tracks inwards - closer together - so that when you get to the point where you *have* to be 5-7mil apart you're already neeearrrrly that far apart *anyway* so it's not so bad.
ok :) that's perfectly doable.
Just a small question. Why not deviate from the 45 degree angle? So you end up with converging lines, instead of the stepped approach?
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On Mon, Dec 11, 2017 at 7:25 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Just a small question. Why not deviate from the 45 degree angle? So you end up with converging lines, instead of the stepped approach?
because the steps are a close approximation to the original 1956 paper which ensures that there is a smooth transition of the impedance.
if you think "microwave guide" and "lamina flow", if you just draw a straight line the signal bounces about and comes straight back at you.
however if you have these specially-arranged steps, it's a bit like a parabolic mirror, the signal bounces in a mathematically very special way that *focusses* the signal onto the (narrower) track, ensuring that it doesn't bounce back at you.
the ideal case would be to have hundreds of steps (not 45 degree ones) and lots of small lines, i'm currently investigating the format of the .ASC files, identifying where the heck you're supposed to put traces.
l.
2017-12-11 11:53 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Mon, Dec 11, 2017 at 7:25 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Just a small question. Why not deviate from the 45 degree angle? So you end up with converging lines, instead of the stepped approach?
because the steps are a close approximation to the original 1956 paper which ensures that there is a smooth transition of the impedance.
I think we're on different tracks here. ;-)
We have different types of impedance and capacitance going on. 1. Single trace (of a pair) - capacitance to other traces/planes such as GND/PWR - impedance due to trace geometry 2. Intra differential trace (between two line of the same pair) - capacitance to the differential trace - Impedance due to the parallel nature of the trace pair 3. Inter differential trace (between different pairs) - capacitance to the differential trace - Impedance due to the parallel nature of the trace pair
So for matching impedance on a single trace you can do a taper. To match different incoming outgoing impedance requirements or to nullify impedance mismatching parts such as vias.
See the left side drawings. The taper can be in steps or smooth. I've read a, recent, paper that the effect is the same. Indeed don't make to great steps as they'll create reflections.
In an inter pair you'll the steps on the outside so the width between the two lines of a pair remains as smooth as possible. Skinning effect in combination with the magnetic fields, which create the capacitance effect, will draw the signal to travel mostly on the inner edges. So the steps don't touch the signal to much.
For narrowing multiple pairs, I cannot see the benefit of a stepped approach. See the left side drawings. Just more work.
On Tue, Dec 12, 2017 at 8:10 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-12-11 11:53 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Mon, Dec 11, 2017 at 7:25 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
Just a small question. Why not deviate from the 45 degree angle? So you end up with converging lines, instead of the stepped approach?
because the steps are a close approximation to the original 1956 paper which ensures that there is a smooth transition of the impedance.
I think we're on different tracks here. ;-)
We have different types of impedance and capacitance going on.
- Single trace (of a pair)
- capacitance to other traces/planes such as GND/PWR
- impedance due to trace geometry
- Intra differential trace (between two line of the same pair)
- capacitance to the differential trace
- Impedance due to the parallel nature of the trace pair
- Inter differential trace (between different pairs)
- capacitance to the differential trace
- Impedance due to the parallel nature of the trace pair
So for matching impedance on a single trace you can do a taper. To match different incoming outgoing impedance requirements or to nullify impedance mismatching parts such as vias.
right, this is inter-pair, and also the keep-out area which must also be tapered. we're leaving individual traces @ 5mil and the calculations that richard's done are all based on traces being fixed @ 5mil.
In an inter pair you'll the steps on the outside so the width between the two lines of a pair remains as smooth as possible.
right. ok. so the paper from 1956 explains that it is REALLY IMPORTANT that you NOT do a straight (linear) taper. the shape of the steps is VERY specific, and is based on studies (many decades later) that explain that you can EMULATE the curving shapes of required tapering from the original paper by deploying a CHAIN of DISCRETE steps.
these discrete steps are what richard went to the trouble of outlining in that table.
For narrowing multiple pairs, I cannot see the benefit of a stepped approach. See the left side drawings. Just more work.
more work with a very very specific and specifically designed outcome, based on a paper that has been demonstrated mathematically to be very specific and precise in how it gradually changes impedance from one value to another whilst GUARANTEEING that at no time will there be ANY reflections back down the line.
a linear step approach such as the one that you outline in the drawing is GUARANTEED 100% to cause reflections.
the gradual change outlined in the 1956 paper is similar to an S curve (not exactly, but close enough). i'm drawing it (attached) freehand on gimp - really badly - so it may not be totally clear. the black lines are supposed to be the smooth S-like tapers of the "ideal" case. the purple one is supposed to be the 45-degree multiple individual steps.
so by doing this series of steps the inter-pair impedance changes from its (appx).... 110 ohms by virtue of the distance being 15mil to each pair and also to the keep-out area, down to something closer to 50 ohms by the time we get to the end of the set of 8 steps, by which point the inter-pair spacing is 5mil, as you have to have, because of the distance between the pads on the ESD and the JAE DC-3 HDMI connector.
if we followed the "straight line" inter-pair approach that you're advocating, the change from the 110 ohms to 50 ohms using linear spacing between 45-turn steps OR a straight 1-line arbitrary-angle taper is *GUARANTEED* to result in reflections back down the line(s).
btw numbers (110, 50) above are not wholly accurate, richard calculated them correctly, i am just substituting convenient indicative numbers from my vague and non-specific memory.
l.
2017-12-12 9:33 GMT+01:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Tue, Dec 12, 2017 at 8:10 AM, mike.valk@gmail.com
so by doing this series of steps the inter-pair impedance changes from its (appx).... 110 ohms by virtue of the distance being 15mil to each pair and also to the keep-out area, down to something closer to 50 ohms by the time we get to the end of the set of 8 steps, by which point the inter-pair spacing is 5mil, as you have to have, because of the distance between the pads on the ESD and the JAE DC-3 HDMI connector.
if we followed the "straight line" inter-pair approach that you're advocating, the change from the 110 ohms to 50 ohms using linear spacing between 45-turn steps OR a straight 1-line arbitrary-angle taper is *GUARANTEED* to result in reflections back down the line(s).
We'll I'm not convinced on the reflections in inter pair matching. But indeed my "linear" might not be the best and results in unequal impedance transitions and thus in signal degradation. But you can stil do gradual corners. See the "transitioned" attachment.
But without a, 3d, simulation or a real world test this is all very theoretical.
btw numbers (110, 50) above are not wholly accurate, richard calculated them correctly, i am just substituting convenient indicative numbers from my vague and non-specific memory.
l.
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On Tue, Dec 12, 2017 at 2:54 PM, mike.valk@gmail.com mike.valk@gmail.com wrote:
We'll I'm not convinced on the reflections in inter pair matching. But indeed my "linear" might not be the best and results in unequal impedance transitions and thus in signal degradation. But you can stil do gradual corners. See the "transitioned" attachment.
yes. the issue i have with the 45-degree thing is that it has to be staggered (you can't make the transitions on *exactly* the same X-distance along the axis because the pairs, during the 45 degree turn, would actually come *too close* by a factor of pow(2,0.5) * 5mil.
a non-45-degree variant - exactly as you draw - would not have that same problem. *but*.... at the same time, 8 steps would not be anything like enough, because of the risk of inaccuracies in the distance between the tracks, perhaps going to 4.95mil separation at the exact point where each track turns. all a pain.
and that's why i said that 100s of such steps would be needed... which i'm not going to do right now, as i would need the actual formulae from the 1956 paper as opposed to richard's hand-calculated 8 steps.
But without a, 3d, simulation or a real world test this is all very theoretical.
the theory - which has had quite some time to mature and be demonstrated to be accurate both in complex electrical simulations (papers doing this were referenced on arxiv.org in the original message that richard sent a few months back) and the real world - has matured over the past 60 years and that's why i'm trusting richard's assessment.
l.
okay! so i've just done a new update which outlines a rather (vague) summary of the taper, there's another update to go out before that, which is nearly there: in the meantime i'm making good progress with the program that reads the ASCII PADS format, displays the tracks (so i can see quickly what's going on), and alters the tracks to create the taper.
attached is like the first version, it requires several adjustments (all of which will be done programmatically).
btw richard: as it's done programmatically this *could* actually use a *much* more accurate algorithm, and a lot more steps.
the steps have to be offset though. they *must* not all be on the same 45 degree line, because if they did then the inter-pair spacing would drop below 5mil, and when they got close to 5 mil separation the *intra*-pair spacing would drop below 5mil. so everything needs to be shuffled up in a cascade that relates (weirdly) to *half* of 45 degrees - 22.5
also it would appear that the horizontal tracks, i turned NE by 45 degrees a little bit too early (i did the tracks by eye) so i have to alter that...
it's klunky but it's getting there.
l.
ok sooOo... here's where i'm at so far:
* from the horizontal separation of the big straight i "virtually" carried them along (or back in the case of TX0 and TXC) so that they meet TX1 (green)
* i then pushed each track starting point out by a set fixed distance such that each pair would be EXACTLY 15mil separation from the others and EXACTLY 5mil separation inter-pair. this was a bit trial-and-error but worked fine
* i then, using the same offset pattern, pushed the starting point diagonally upwards, and also added something like 30 mil to the start position to move the end point closer towards the end.
now, just to emphasise the problem i'm focussing on at the moment i've reduced each 45-degree step from its proposed 15mil right down to 1mil. you can now see clearly that there are two problems:
(1) with the exact same starting offset the intra-pair separation, which should be EXACTLY 5mil, clearly isn't. i need to add in an extra offset of... um... i don't know exactly, it's probably sin(22.5) * 5.0 or something.
(2) whilst TX2 and TX0 are being adjusted fine, TXC is "racing ahead". this is because the amount that TXC is supposed to come in is DOUBLE that of TX2 and TX0. so i doubled the 45 degree thing and then added on a FIXED amount (15 mil) but it seems i forgot you'd be supposed to subtract the 45 degree turning amount FROM the fixed amount, such that the... you get the idea i'm sure.
anyway it should be fairly clear that there would be no way in seven hells that this would be at all practical without doing it entirely in software. at least thee *fundamental* flaws in my understanding of how this should and could be done have been uncovered just in the past 2 days alone, each of which would have been SEVERAL DAYS of f*****g about with manual PADS track layout.
l.
... yyyyeahhh.... that looks better, doesn't it?
the left outer track is shuffled forward by... errr.... sqrt(2) / 4 * 5mil the one in from that (HTX2P) doesn't need shuffling as it's right next to the green pair... the right outer one (HTXCN) by 3x that amount the next one in (HTXCP) by 2x that amount the next one in (HTX0N) by 1x that amount HTX0P is right next to the green pair which is dead-straight so doesn't need shuffling
so if i've got this right, the separation gap intra-pair should remain at 5.0 mil, and when all the pairs get close together at the end they should again be exactly 5.0 mil apart even on the 45 degree bending.
whewwww :)
i think that's it (oh, except the step needs adjusting to 15mil not 5mil as it is now). now i have to identify where in the PADS file the rectangle for the keepout area is, add *that* to the parser as well, then do the same maths and create a tethered keepout area. *sigh*...
l.
On Sat, Dec 16, 2017 at 10:12 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
... yyyyeahhh.... that looks better, doesn't it?
Strong work, Luke! That does indeed look nice.
the left outer track is shuffled forward by... errr.... sqrt(2) / 4 * 5mil the one in from that (HTX2P) doesn't need shuffling as it's right next to the green pair... the right outer one (HTXCN) by 3x that amount the next one in (HTXCP) by 2x that amount the next one in (HTX0N) by 1x that amount HTX0P is right next to the green pair which is dead-straight so doesn't need shuffling
so if i've got this right, the separation gap intra-pair should remain at 5.0 mil, and when all the pairs get close together at the end they should again be exactly 5.0 mil apart even on the 45 degree bending.
whewwww :)
i think that's it (oh, except the step needs adjusting to 15mil not 5mil as it is now). now i have to identify where in the PADS file the rectangle for the keepout area is, add *that* to the parser as well, then do the same maths and create a tethered keepout area. *sigh*...
I'm sorry I didn't fill in more of the geometric considerations. Looks like you have them in hand.
When the step offset is d, then the 45 degree step travel will be sqrt(2.0) * d.
Looks like you have the starting positions parallel which was the intent but I did not specify the mathematics. I didn't know what origin or reference point and direction you would like to use.
On Mon, Dec 18, 2017 at 3:55 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sat, Dec 16, 2017 at 10:12 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
... yyyyeahhh.... that looks better, doesn't it?
Strong work, Luke! That does indeed look nice.
:)
i think that's it (oh, except the step needs adjusting to 15mil not 5mil as it is now). now i have to identify where in the PADS file the rectangle for the keepout area is, add *that* to the parser as well, then do the same maths and create a tethered keepout area. *sigh*...
I'm sorry I didn't fill in more of the geometric considerations. Looks like you have them in hand.
in drunken-walk programming style .... yyyeah :)
When the step offset is d, then the 45 degree step travel will be sqrt(2.0) * d.
Looks like you have the starting positions parallel which was the intent but I did not specify the mathematics. I didn't know what origin or reference point and direction you would like to use.
i had the picture you drew memorised in my mind and realised the mistake.
so... ah.... key question here... is the taper needed or not? :) should i instead be just setting 15mil clearance all round? (and put a GND keepout underneath the ESD)?
l.
On Sun, Dec 17, 2017 at 9:05 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
so... ah.... key question here... is the taper needed or not? :)
The taper is a nice idea for changing the context smoothly but it requires enough space that we can't return to our original context before the cable connector (which is specified to be 100 Ohms). So I think we're better off living with the small, brief discontinuities due to incursions into our design geometrical constraints, than introducing a hulking change in our design geometrical constraints to cover up the incursions (with the likely effect of changing our impedance) and having no space left to taper the new impedance to 100 Ohm at the connector.
should i instead be just setting 15mil clearance all round? (and put a GND keepout underneath the ESD)?
Are there signals beneath the ESD components on layer 3 or 4? If not, we could put our ground reference planes on those layers under the ESD components which would move them both one layer deeper. (We already have several conveniently placed ground vias.) Otherwise, I would just copy the lands for the ESD pads connected to the high-speed signals and put them as ground keepouts on the normal ground reference planes. (In other words, only keep out the copper on the reference plane just under the signal path where it goes through a wide pad for the ESD component.)
Likewise with the connector, I would put a ground keep out under the lands on layer 2 (probably best to just draw a keepout under the whole connector on layer 2) but allow layer 5 to provide a full ground shield. (Provided my assumption is correct that the connector is soldered on layer 1.)
On Sun, Dec 17, 2017 at 9:05 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
should i instead be just setting 15mil clearance all round?
I would suggest trying to maintain 15mil clearance when possible. But it is not the end of the world if it can't be maintained--especially over short distances.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Dec 18, 2017 at 5:23 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 9:05 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
should i instead be just setting 15mil clearance all round?
I would suggest trying to maintain 15mil clearance when possible. But it is not the end of the world if it can't be maintained--especially over short distances.
ok cool.
Sorry for my long response times the last several weeks. I added choir director to my collection of hats, 6 rehearsals, and performed 3 carols at the Christmas program on the 9th. I performed a piano trio arrangement of a carol with my daughters on the 9th (Christmas program) and 16th (cello recital). I accompanied 3 chamber groups at their Fall final concert on the 13th. I accompanied 4 elementary school string orchestras at a fundraiser on the 15th. I played the organ for a church service on the 16th. This week looks to be a lot slower: my daughter only has one concert, I have a choir rehearsal and to organize a piano trio or quartet for this weekend.
On Mon, Dec 18, 2017 at 5:45 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Sorry for my long response times the last several weeks. I added choir director to my collection of hats,
:)
6 rehearsals, and performed 3 carols at the Christmas program on the 9th. I performed a piano trio arrangement of a carol with my daughters on the 9th (Christmas program) and 16th (cello recital). I accompanied 3 chamber groups at their Fall final concert on the 13th. I accompanied 4 elementary school string orchestras at a fundraiser on the 15th. I played the organ for a church service on the 16th. This week looks to be a lot slower: my daughter only has one concert, I have a choir rehearsal and to organize a piano trio or quartet for this weekend.
nice! when i was in cambridge i joined a choir and formed a medieval music group. interestingly because of that i gained both perfect pitch *and* the ability to tell the time to the minute (lost now). i used to confuse the hell of of people asking me for the time, being able to respond correctly and instantly... they'd go and ask someone else and get the exact same answer :)
the choir was open access (no auditions), you just turned up, which a lot of people liked: no cliques, no pressure. we did Handel's Messiah jaezzuss we made a hell of an impression: five HUNDRED people and a full orchestra. it was aweesome. the next one we did Mozart's Requiem and that one... how does it go.. "Verbegaal auu tre-ooo (tres haut)..." it's the one the mice sing in the film "Babe"... :)
yeah. i miss singing.
l.
On Mon, Dec 18, 2017 at 5:16 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 9:05 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
so... ah.... key question here... is the taper needed or not? :)
The taper is a nice idea for changing the context smoothly but it requires enough space that we can't return to our original context before the cable connector (which is specified to be 100 Ohms). So I think we're better off living with the small, brief discontinuities due to incursions into our design geometrical constraints, than introducing a hulking change in our design geometrical constraints to cover up the incursions (with the likely effect of changing our impedance) and having no space left to taper the new impedance to 100 Ohm at the connector.
aw poop! i went to all the trouble of writing a parser for PADS :)
should i instead be just setting 15mil clearance all round? (and put a GND keepout underneath the ESD)?
Are there signals beneath the ESD components on layer 3 or 4?
it seems i am sensible enough not to have done that :)
If not, we could put our ground reference planes on those layers under the ESD components which would move them both one layer deeper. (We already have several conveniently placed ground vias.) Otherwise, I would just copy the lands for the ESD pads connected to the high-speed signals and put them as ground keepouts on the normal ground reference planes.
makes sense to me
(In other words, only keep out the copper on the reference plane just under the signal path where it goes through a wide pad for the ESD component.)
including the 5 mil track *between* the ESD pads, or excluding that? so literally just the ESD pads, yeah?
Likewise with the connector, I would put a ground keep out under the lands on layer 2 (probably best to just draw a keepout under the whole connector on layer 2)
including for the HSCL, HHPD and even the GND pads? of course there's VIAs connecting the tracks in between the diff-pairs
but allow layer 5 to provide a full ground shield. (Provided my assumption is correct that the connector is soldered on layer 1.)
it is.
l.
On Sun, Dec 17, 2017 at 10:28 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
aw poop! i went to all the trouble of writing a parser for PADS :)
That is pretty cool. Now you have a way to algorithmically generate traces. I'm sorry we didn't need it, yet.
Are there signals beneath the ESD components on layer 3 or 4?
it seems i am sensible enough not to have done that :)
If not, we could put our ground reference planes on those layers under the ESD components which would move them both one layer deeper. (We already have several conveniently placed ground vias.)
So it might be easier to just put a ground keepout on layer 2 under the ESD component on layer 1 and a corresponding ground fill on layer 3. Likewise a ground keepout on layer 5 under the ESD component(s) on layer 6 and a corresponding ground fill on layer 4.
(The "otherwise" case below is given in case you feel more comfortable putting keepouts on layers 2 and 5 than changing layers 3 and 4.)
Otherwise, I would just copy the lands for the ESD pads connected to the high-speed signals and put them as ground keepouts on the normal ground reference planes.
makes sense to me
(In other words, only keep out the copper on the reference plane just under the signal path where it goes through a wide pad for the ESD component.)
including the 5 mil track *between* the ESD pads, or excluding that? so literally just the ESD pads, yeah?
I was recommending just under the ESD pads specifically for the high-frequency differential signals.
Likewise with the connector, I would put a ground keep out under the lands on layer 2 (probably best to just draw a keepout under the whole connector on layer 2)
including for the HSCL, HHPD and even the GND pads? of course there's VIAs connecting the tracks in between the diff-pairs
Wouldn't have to I suppose but the idea is to move the ground further away from the high-frequency pads to reduce the capacitive coupling thus increasing the impedance. Thus I think it's probably best to extend the layer 2 keepout under the whole connector.
but allow layer 5 to provide a full ground shield. (Provided my assumption is correct that the connector is soldered on layer 1.)
it is.
Yay!
On Mon, Dec 18, 2017 at 6:03 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So it might be easier to just put a ground keepout on layer 2 under the ESD component on layer 1 and a corresponding ground fill on layer 3. Likewise a ground keepout on layer 5 under the ESD component(s) on layer 6 and a corresponding ground fill on layer 4.
yehyeh. ah.... do you mean the *whole* component? conflicts with putting keepout(s) under individual pads...
I was recommending just under the ESD pads specifically for the high-frequency differential signals.
conflicts with words above about "GND keepout under ESD components"...
Likewise with the connector, I would put a ground keep out under the lands on layer 2 (probably best to just draw a keepout under the whole connector on layer 2)
including for the HSCL, HHPD and even the GND pads? of course there's VIAs connecting the tracks in between the diff-pairs
Wouldn't have to I suppose but the idea is to move the ground further away from the high-frequency pads to reduce the capacitive coupling thus increasing the impedance. Thus I think it's probably best to extend the layer 2 keepout under the whole connector.
got it.
l.
On Sun, Dec 17, 2017 at 11:20 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 6:03 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So it might be easier to just put a ground keepout on layer 2 under the ESD component on layer 1 and a corresponding ground fill on layer 3. Likewise a ground keepout on layer 5 under the ESD component(s) on layer 6 and a corresponding ground fill on layer 4.
yehyeh. ah.... do you mean the *whole* component? conflicts with putting keepout(s) under individual pads...
I was recommending just under the ESD pads specifically for the high-frequency differential signals.
conflicts with words above about "GND keepout under ESD components"...
Sorry for the misunderstanding. I wasn't very clear about delineating the difference between two options for dealing with the ESD component pads. 1. Ground keepout under whole ESD component(s) on adjacent reference ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent). 2. Ground keepouts under just high-frequency signal pads of ESD components on adjacent reference ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6).
Clear as mud?
On Mon, Dec 18, 2017 at 6:31 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Sorry for the misunderstanding. I wasn't very clear about delineating the difference between two options for dealing with the ESD component pads.
i was wondering which one to deploy.
- Ground keepout under whole ESD component(s) on adjacent reference
ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent). 2. Ground keepouts under just high-frequency signal pads of ESD components on adjacent reference ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6).
Clear as mud?
clear... except which one to actually deploy :)
l.
On Sun, Dec 17, 2017 at 11:34 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 6:31 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Ground keepout under whole ESD component(s) on adjacent reference
ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent). 2. Ground keepouts under just high-frequency signal pads of ESD components on adjacent reference ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6).
Clear as mud?
clear... except which one to actually deploy :)
Well, I read about #2 in the TI High-Speed Layout but I like #1 better because we have high-frequency signals in parallel on both sides of the board and I'd feel better because I expect less cross-talk with #1. #1 is a hybrid where we double the distance to the reference ground plane but still have ground shield between high-frequency signals that would otherwise want to radiate/couple.
On Mon, Dec 18, 2017 at 7:02 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 11:34 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 6:31 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Ground keepout under whole ESD component(s) on adjacent reference
ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent).
clear... except which one to actually deploy :)
Well, I read about #2 in the TI High-Speed Layout but I like #1 better because we have high-frequency signals in parallel on both sides of the board and I'd feel better because I expect less cross-talk with #1. #1 is a hybrid where we double the distance to the reference ground plane but still have ground shield between high-frequency signals that would otherwise want to radiate/couple.
yehyeh, makes sense to me. okay! it's also much more straightforward.
l.
On Mon, Dec 18, 2017 at 3:02 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 7:02 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 11:34 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 6:31 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Ground keepout under whole ESD component(s) on adjacent reference
ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent).
clear... except which one to actually deploy :)
Well, I read about #2 in the TI High-Speed Layout but I like #1 better because we have high-frequency signals in parallel on both sides of the board and I'd feel better because I expect less cross-talk with #1. #1 is a hybrid where we double the distance to the reference ground plane but still have ground shield between high-frequency signals that would otherwise want to radiate/couple.
yehyeh, makes sense to me. okay! it's also much more straightforward.
After sleeping on it, I'd recommend making the new, deeper ground fill slightly larger (~5mil? margin) than the ground keepout on the original reference plane--as long as that's not too hard to accomplish.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Mon, Dec 18, 2017 at 2:55 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Mon, Dec 18, 2017 at 3:02 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 7:02 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Sun, Dec 17, 2017 at 11:34 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 6:31 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Ground keepout under whole ESD component(s) on adjacent reference
ground plane (layer 2 for ESD on layer 1, layer 5 for ESD on layer 6), ground fill on deeper layer (layer 3 for ESD on layer 1, layer 4 for ESD on layer 6). Ground fills connected as always using vias (some probably already adjacent).
clear... except which one to actually deploy :)
Well, I read about #2 in the TI High-Speed Layout but I like #1 better because we have high-frequency signals in parallel on both sides of the board and I'd feel better because I expect less cross-talk with #1. #1 is a hybrid where we double the distance to the reference ground plane but still have ground shield between high-frequency signals that would otherwise want to radiate/couple.
yehyeh, makes sense to me. okay! it's also much more straightforward.
After sleeping on it, I'd recommend making the new, deeper ground fill slightly larger (~5mil? margin) than the ground keepout on the original reference plane--as long as that's not too hard to accomplish.
um... um.... noo shouuuld be fiiine.... niggles: from the last picture you can see i have HHPD coming in at the top. and also i remembered, pin 19 is 5V power, that's coming in (big track, green) on Layer 4. however.... Layer 5 and 3 would have GND surround it, so that's ok.
l.
On Dec 18, 2017, at 08:27, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Mon, Dec 18, 2017 at 2:55 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
After sleeping on it, I'd recommend making the new, deeper ground fill slightly larger (~5mil? margin) than the ground keepout on the original reference plane--as long as that's not too hard to accomplish.
In this case I was speaking of what I had quoted above this excerpt in its original context which was the treatment of traces beneath the ESD components (not the connector). In fact the trace in the middle of each ESD component is ground and is connected to other ground layers by several vias. Under that trace we might as well have a ribbon of ground plane on layers 2 and 5.
um... um.... noo shouuuld be fiiine.... niggles: from the last picture you can see i have HHPD coming in at the top. and also i remembered, pin 19 is 5V power, that's coming in (big track, green) on Layer 4. however.... Layer 5 and 3 would have GND surround it, so that's ok.
Looks fine. As long as the high-frequency pins of the connector land on layer 1 with an unobstructed view of the ground plane on layer 5, I think we will have achieved our goal (moving the ground plane deeper in order to try and maintain ~100Ω differential impedance).
okaay, so this is what i've done: expanded the layer 1 keepout (manually) to as near to 15mil as i can get. then added 2 keepouts on layers 2 and 5. the line on the right is the board edge, so it goes *right* out: the connector shield is there, i figure it can catch EMI. plus there's layers 3 and 4 GND plane.
layer 5 is over BOTTOM (6, blue), that one i made just a rectangle, extending out an extra 5 mil. however there's obviously VIAs in it which... really... why make it 5 mil beyond and you still have those VIAs? also, should i put a horizontal track across on Layer 5, say 10mil wide, between the 3 GND vias down the middle?
layer 2 is under TOP (1, red), the shape is a little more... slightly messy, it goes round the connector (again extending right out over the board edge, otherwise not enough space to maintain 15mil clearance), and this time because there *is* no keepout area on layer 6 (should there be one? i think i should, really.... hmmmm.) i brought the keepout to within 15 mil of the ESD...
hmmm... i'll add an extra keepout area around where those red (layer 1) tracks are, i think.
thoughts / corrections appreciated
l.
On Tue, Dec 19, 2017 at 11:40 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
okaay, so this is what i've done: expanded the layer 1 keepout (manually) to as near to 15mil as i can get.
Sounds good. I think this would be a good thing for both the TOP (layer 1, red) and BOTTOM (layer 6, blue) along the path of the high-frequency signals (differential pairs). I see it on the BOTTOM but not from the vias towards the ESD component on the TOP? We know ahead of time there will be things that can't move outside the keepout but it will at least keep the ground fill at bay.
then added 2 keepouts on layers 2 and 5. the line on the right is the board edge, so it goes *right* out: the connector shield is there, i figure it can catch EMI. plus there's layers 3 and 4 GND plane.
layer 5 is over BOTTOM (6, blue), that one i made just a rectangle, extending out an extra 5 mil. however there's obviously VIAs in it which... really... why make it 5 mil beyond and you still have those VIAs? also, should i put a horizontal track across on Layer 5, say 10mil wide, between the 3 GND vias down the middle?
layer 2 is under TOP (1, red), the shape is a little more... slightly messy, it goes round the connector (again extending right out over the board edge, otherwise not enough space to maintain 15mil clearance), and this time because there *is* no keepout area on layer 6 (should there be one? i think i should, really.... hmmmm.) i brought the keepout to within 15 mil of the ESD...
hmmm... i'll add an extra keepout area around where those red (layer
- tracks are, i think.
thoughts / corrections appreciated
Good work, Luke! Let me try to clarify my recommendations as they seem to have been mixed into one formula:
1. Around high-frequency differential pairs (regardless of layer) try to maintain ~10mil keepout for at least the ground fill in the same layer (BOTTOM = layer 6, blue; TOP = layer 1, red) from the ground and signal vias to the connector. Then terminate the keepout (let it go to the 5mil rule) around the connector on TOP=layer 1. This is a nod to the fact that the spacing of pads is very close anyway.
2. Under ESD components with high-frequency differential pairs: i. I would connect the ground vias along the center ground track on every layer with a 10mil track, if not ground plane or fill. ii. I would create a void in the close ground plane (layer 2 for the ESD component on TOP=layer 1, layer 5 for the ESD component on BOTTOM=layer 6) under the path (pads) of the high-frequency differential pairs. One keepout/void for each differential pair in light of (i) above. iii. On the next deeper layer (layer 3 for the ESD component on TOP=layer 1, layer 4 for the ESD component on BOTTOM=layer 6) create a ground fill connected, if possible to the ground vias in the center of the ESD component and the vias at the corners.
3. Under the high-frequency connector pads, a keepout on layer 2 (3 and 4) ground fill. The intent is that under the HTX?{P|N} connector pads no copper till layer 5 ground fill.
Attached pictures hopefully elucidate the situation. Let me know if anything seems amiss or you have any questions.
As soon as I sent the last message with the pictures, I realized I hadn't drawn the ground keepout for layers 2,3,4 under the connector. So here's the updated picture.
On Wed, Dec 20, 2017 at 7:58 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
As soon as I sent the last message with the pictures, I realized I hadn't drawn the ground keepout for layers 2,3,4 under the connector. So here's the updated picture.
ok cool the pictures i dig :) yes i was thinking similar separation (cyan drawing) with a 10mil horizontal track. on it...
http://hands.com/~lkcl/eoma/a20/275_hdmi/
ok so this is four pictures, i did flood-fill, i'm going to update them incrementally, for example layer 1 in between the 2 points where the flood-fill keepout is too narrow to let it in (the maximum "curve" is something like 11 mil diameter) i've expanded that to let it in. also layer5 the horizontal track doesn't reach all the way over. the layer2 one i don't exactly know what to do, there's no VIA nearby (and i can't fit one either).
this is a pain! i might see if i can set a clearance to GND on individual tracks / connections as opposed to NETs.
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 22, 2017 at 8:54 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
http://hands.com/~lkcl/eoma/a20/275_hdmi/
ok so this is four pictures, i did flood-fill, i'm going to update them incrementally, for example layer 1 in between the 2 points where the flood-fill keepout is too narrow to let it in (the maximum "curve" is something like 11 mil diameter) i've expanded that to let it in. also layer5 the horizontal track doesn't reach all the way over. the layer2 one i don't exactly know what to do, there's no VIA nearby (and i can't fit one either).
this is a pain! i might see if i can set a clearance to GND on individual tracks / connections as opposed to NETs.
ok that worked. just uploading a video here:
turns out that there's a feature i'd not used before, called "conditional rules". you can specify that *if* GND meets HDMI Group, clearance rules shall be different. ordinarily you have to forcibly set the *entire* GND plane to specific clearances (to ALL objects), or the *entire* HDMI group to specific clearances (to ALL objects)... this "conditional" rule does the trick.
richard i go over it in the video but i believe the layer... 5 keepout needs to also be extended under the layer 6 (blue, bottom) tracks leading to the VIAs that jump up to the DC3 connector pads. also i believe that i should be adding some tracks (pink) which, particularly if there is to be a hole in layer 5 underneath, should be around a 5 mil clearance, to match the fact that it's swapping vertical distance for horizontal distance, what do you think?
l.
On Dec 22, 2017, at 07:51, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Dec 22, 2017 at 8:54 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
[…]
this is a pain! i might see if i can set a clearance to GND on individual tracks / connections as opposed to NETs.
ok that worked. just uploading a video here:
turns out that there's a feature i'd not used before, called "conditional rules". you can specify that *if* GND meets HDMI Group, clearance rules shall be different. ordinarily you have to forcibly set the *entire* GND plane to specific clearances (to ALL objects), or the *entire* HDMI group to specific clearances (to ALL objects)... this "conditional" rule does the trick.
Nice work! That certainly simplifies things!
richard i go over it in the video but i believe the layer... 5 keepout needs to also be extended under the layer 6 (blue, bottom) tracks leading to the VIAs that jump up to the DC3 connector pads. also i believe that i should be adding some tracks (pink) which, particularly if there is to be a hole in layer 5 underneath, should be around a 5 mil clearance, to match the fact that it's swapping vertical distance for horizontal distance, what do you think?
I believe that the right thing is to not extend the layer 5 ground keepout under the differential nets on their way out to the connector because it is the ground plane for layer 6. The reason for dropping the ground plane under the connector pins (layer 1) from layer 2 to layer 5 is that the pins are so close to each other. But we are still interested in the shielding effect of ground plane below the high-frequency signals (on the differential pairs) on layer 1 and between the signals on layer 1 and those sneaking under on layer 6. That's my reason for keeping layer 5 ground fill everywhere except under the layer 6 high-frequency pads of the ESD (where he drop to ground on layer 4).
Here's another view of the connector end with some slight revisions of the ground fill and keepout boundaries between the ESD and connector components.
Summary:
1. I moved the East extent of the layer 3 ground fill east to the edge of the connector pads. 2. The layer 2 ground keepout remains open under the high-frequency pads of both the ESD component and the connector. 3. The layer 2,3,4 ground keepout West edge moved with the East edge of the layer 3 ground fill to the edge of the connector pads.
Thanks for the images and video, Luke.
Basically, this change is an attempt to drop from layer 1 microstrips over layer 2 ground in the normal transmission line to layer 1 microstrips over layer 3 ground as we pass through the ESD component layout and on to the connector at which point we transition to layer 1 pads (close spacing) over layer 5 ground.
On the other side we have layer 6 microstrips over layer 5 ground in the normal transmission line. We transition to layer 6 microstrips over layer 4 ground as we pass through the ESD component layout. We move back to layer 6 microstrips over layer 5 ground on the way to the vias that will connect us to layer 1 connector pads.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 22, 2017 at 10:32 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here's another view of the connector end with some slight revisions of the ground fill and keepout boundaries between the ESD and connector components.
Summary:
- I moved the East extent of the layer 3 ground fill east to the
edge of the connector pads.
ok remember that ground flood-fill is the entire layer 3, i'm not creating a *specific* area for ground "fill", it's done by default according to the (specified) design rules. with the new "conditional" rule added, layer 3 now looks like this: http://hands.com/~lkcl/eoma/a20/275_hdmi/layer3.jpg
so there's a few things i need to sort out, which i'll get to: main reason for showing that image is: the clearance to the VIAs has also extended to 15mil now. i believe it's not so much the vias though as the tracks connected *to* the vias. if there has to be a 5 mil clearance to those i can... maybe sort something out :)
- The layer 2 ground keepout remains open under the high-frequency
pads of both the ESD component and the connector.
ok cool.
- The layer 2,3,4 ground keepout West edge moved with the East edge
of the layer 3 ground fill to the edge of the connector pads.
oh wait... i haven't put in a keepout *at all* on layers 3 and 4. you think it would be best to punch the hole *right* down so that it's only layer 5 providing a GND plane for both sides? it makes sense, i just want to confirm.
Thanks for the images and video, Luke.
ehn the vides are fun :)
l.
On Dec 22, 2017, at 20:38, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Dec 22, 2017 at 10:32 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here's another view of the connector end with some slight revisions of the ground fill and keepout boundaries between the ESD and connector components.
Summary:
- I moved the East extent of the layer 3 ground fill east to the
edge of the connector pads.
ok remember that ground flood-fill is the entire layer 3, i'm not creating a *specific* area for ground "fill", it's done by default according to the (specified) design rules. with the new "conditional" rule added, layer 3 now looks like this: http://hands.com/~lkcl/eoma/a20/275_hdmi/layer3.jpg
so there's a few things i need to sort out, which i'll get to: main reason for showing that image is: the clearance to the VIAs has also extended to 15mil now. i believe it's not so much the vias though as the tracks connected *to* the vias. if there has to be a 5 mil clearance to those i can... maybe sort something out :)
15mil clearance to HDMI nets and vias won't hurt anybody's feelings! Looks good (minus the keepout under the connector).
[…]
- The layer 2,3,4 ground keepout West edge moved with the East edge
of the layer 3 ground fill to the edge of the connector pads.
oh wait... i haven't put in a keepout *at all* on layers 3 and 4. you think it would be best to punch the hole *right* down so that it's only layer 5 providing a GND plane for both sides? it makes sense, i just want to confirm.
Yes, that is what I was asking for under the high-frequency differential signals at the connector. If you have reservations about it, let me know. I'm happy to get feedback from another perspective.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Dec 23, 2017 at 4:26 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
15mil clearance to HDMI nets and vias won't hurt anybody's feelings!
:)
[…]
- The layer 2,3,4 ground keepout West edge moved with the East edge
of the layer 3 ground fill to the edge of the connector pads.
oh wait... i haven't put in a keepout *at all* on layers 3 and 4. you think it would be best to punch the hole *right* down so that it's only layer 5 providing a GND plane for both sides? it makes sense, i just want to confirm.
Yes, that is what I was asking for under the high-frequency differential signals at the connector. If you have reservations about it, let me know.
nope, sounds good to me. i Get It.
l.
ok next one :)
i updated the links, http://hands.com/~lkcl/eoma/a20/275_hdmi/ 6 layer screenshots this time
main thing is, i thiiink... there's a way for EMI to escape through the holes in layer 5 (under ESD) on the east end, into the west end of the layer 4 hole (under connector), what do you think?
also you can see, at points in the video (i'll go over it myself when doing changes), i have to adapt the shape on layer... 6 to match the (new, 15mil) clearance between HDMI tracks and GND, i'll do that...
l.
Thanks again for the pictures and the video.
Concerning the keepouts under the connector: 1. At the north boundary I would pull the edge up a little further north away from the northwestern differential pair.
2. At the west boundary I see your point regarding layers 4 and 5. Looks like you have made a good solution. I suppose you could add 5mil additional overlap. How much overlap does it currently have? How much opening from the edge of the keepout on layer 4 to the edge of the closest connector pads?
I would vote to keep the layer 5 holes under the layer 6 ESD pads for the same reason we added them to layer 2 for the ESD pads on layer 1.
Some of the adjustments on layer 6 might be taken care of by modifying the net groups to create an "HDMI High-Frequency" group which contains only the differential pairs {HTX2P, HTX2N, HTX1P, HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional clearance rule to that group. Then see what issues remain.
On Sun, Dec 24, 2017 at 10:29 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Thanks again for the pictures and the video.
no problem
Concerning the keepouts under the connector:
- At the north boundary I would pull the edge up a little further north away from the northwestern differential pair.
oh! ha, i just made it the opposite direction :) reason: HHPD acts (kinda) as a GND for that top (HTX2P) and when i did the flood-fill it looked really weird. i'm switching to a couple of different viewing styles (one of them is actually the gerbers, there's an "X-Ray" option.
the top 2 VIAs right next to HTX2P are too far away, and the 15mil-to-GND-keepout condition makes things unbalanced. see proposed GREEN new via placements and YELLOW track to correct that.
when i show X-ray-mode gerbers layers 1 & 2 i mark in yellow at top a proposed modification, look good? you can see to pin 4 there is that GND via, the shape of the hole gets really weird / sharp edges there.
also i'm aware that the layer 2 and 5 bottom-most curved-shaped-keepout-holes are about 1 mil too far to the left, see yellow (SE corner) where i'll move them both over.
- At the west boundary I see your point regarding layers 4 and 5.
Looks like you have made a good solution. I suppose you could add 5mil additional overlap. How much overlap does it currently have?
currently arouuund 9mil roughly.
How much opening from the edge of the keepout on layer 4 to the edge of the closest connector pads?
around 4mil. tracks are 5mil so can use that as a scale.
I would vote to keep the layer 5 holes under the layer 6 ESD pads for the same reason we added them to layer 2 for the ESD pads on layer 1.
yehyeh.
Some of the adjustments on layer 6 might be taken care of by modifying the net groups to create an "HDMI High-Frequency" group which contains only the differential pairs {HTX2P, HTX2N, HTX1P, HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional clearance rule to that group.
that's what's already done :)
oh, except to VIAs i kept it at 5mil, now i remember. 15 mil to landing pads, 15 mil to tracks, 5mil to VIAs i think this was because i didn't want the holes made by VIAs to be too large. what you think? make them 15mil too?
l.
oh - happy christmas everyone btw :)
should be available by the time this goes out, currently uploading. i'm using actual gerber files (gerbv) to illustrate, as it is slightly different and in some ways easier to visually interpret. i haven't used that up until now as it's an extra step in the process.
richard if you need screenshots in order to properly illustrate particular changes (describing them in words i find isn't quite enough!) just ask, i can make them available.
l.
On Dec 25, 2017, at 05:52, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sun, Dec 24, 2017 at 10:29 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Concerning the keepouts under the connector:
- At the north boundary I would pull the edge up a little further north away from the northwestern differential pair.
oh! ha, i just made it the opposite direction :) reason: HHPD acts (kinda) as a GND for that top (HTX2P) and when i did the flood-fill it looked really weird. i'm switching to a couple of different viewing styles (one of them is actually the gerbers, there's an "X-Ray" option.
Looks like a good resolution of the issue.
the top 2 VIAs right next to HTX2P are too far away, and the 15mil-to-GND-keepout condition makes things unbalanced. see proposed GREEN new via placements and YELLOW track to correct that.
I see how it is unbalanced with respect to the two differential pairs--the outside conductors had close to 15mil clearance to ground but the inside conductors had only the distance to the next pad (which was considerably less, ~7mil?). So I applaud the change to make it more symmetric.
when i show X-ray-mode gerbers layers 1 & 2 i mark in yellow at top a proposed modification, look good? you can see to pin 4 there is that GND via, the shape of the hole gets really weird / sharp edges there.
I'm not seeing the weird / sharp edges so you must have fixed them?
also i'm aware that the layer 2 and 5 bottom-most curved-shaped-keepout-holes are about 1 mil too far to the left, see yellow (SE corner) where i'll move them both over.
Again, I'm not seeing a problem so you must have fixed it.
- At the west boundary I see your point regarding layers 4 and 5.
Looks like you have made a good solution. I suppose you could add 5mil additional overlap. How much overlap does it currently have?
currently arouuund 9mil roughly.
How much opening from the edge of the keepout on layer 4 to the edge of the closest connector pads?
around 4mil. tracks are 5mil so can use that as a scale.
In that case I think you have done enough. The overlap looks good.
Some of the adjustments on layer 6 might be taken care of by modifying the net groups to create an "HDMI High-Frequency" group which contains only the differential pairs {HTX2P, HTX2N, HTX1P, HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional clearance rule to that group.
that's what's already done :)
oh, except to VIAs i kept it at 5mil, now i remember. 15 mil to landing pads, 15 mil to tracks, 5mil to VIAs i think this was because i didn't want the holes made by VIAs to be too large. what you think? make them 15mil too?
I'm not as worried about the holes left by the vias on the east (connector) end as the west (processor) end of the differential pairs if we expanded clearance to 15mil. I'm guessing we have more current flowing through layers 2,4,5 over there. I guess the question boils down to, "Where are the power sources and sinks (including decoupling capacitors) relative to the HDMI high-frequency signal vias?" If the vias make holes on a line connecting power sources to sinks, then we need to either make sure there is plenty of copper providing a path around the holes or minimize the size of the holes.
On Wed, Dec 27, 2017 at 8:51 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
when i show X-ray-mode gerbers layers 1 & 2 i mark in yellow at top a proposed modification, look good? you can see to pin 4 there is that GND via, the shape of the hole gets really weird / sharp edges there.
I'm not seeing the weird / sharp edges so you must have fixed them?
i think so... you checked the video? i''ll do a close-up tomorrow (5am here now)
also i'm aware that the layer 2 and 5 bottom-most curved-shaped-keepout-holes are about 1 mil too far to the left, see yellow (SE corner) where i'll move them both over.
Again, I'm not seeing a problem so you must have fixed it.
- At the west boundary I see your point regarding layers 4 and 5.
Looks like you have made a good solution. I suppose you could add 5mil additional overlap. How much overlap does it currently have?
currently arouuund 9mil roughly.
How much opening from the edge of the keepout on layer 4 to the edge of the closest connector pads?
around 4mil. tracks are 5mil so can use that as a scale.
In that case I think you have done enough. The overlap looks good.
whewwww :)
Some of the adjustments on layer 6 might be taken care of by modifying the net groups to create an "HDMI High-Frequency" group which contains only the differential pairs {HTX2P, HTX2N, HTX1P, HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional clearance rule to that group.
that's what's already done :)
oh, except to VIAs i kept it at 5mil, now i remember. 15 mil to landing pads, 15 mil to tracks, 5mil to VIAs i think this was because i didn't want the holes made by VIAs to be too large. what you think? make them 15mil too?
I'm not as worried about the holes left by the vias on the east (connector) end as the west (processor) end of the differential pairs if we expanded clearance to 15mil. I'm guessing we have more current flowing through layers 2,4,5 over there. I guess the question boils down to, "Where are the power sources and sinks (including decoupling capacitors) relative to the HDMI high-frequency signal vias?" If the vias make holes on a line connecting power sources to sinks, then we need to either make sure there is plenty of copper providing a path around the holes or minimize the size of the holes.
i'll check it again tomorrow but the 5VDC runs along layer 4 right underneath the HDMI long E-W traces. layer 4 3V3 plane was a dog's dinner mess that i had to tidy up last year, and, actually, removing the legacy TSSOP-48 NAND finally actually allowed me to adjust things so that it wasn't a total swiss cheese.
in geeeneral i'm happy with the power / GND layout, i've been paying attention to it.
l.
ok so this, richard, is the point i was talking about, yellow arrow. the purple area was formerly too far to the left, leaving a very weird shape that i wasn't happy with.
all good. ok i'll move on to checking the ground planes and power planes. PADS has this annoying habit of, when you join up two tracks, it goes "oh that completes a loop... i'll just do the job of tidying it up by DELETING all those GND VIAs you so carefully put in..."
nggggh so you have to keep an eye out for that :)
l.
ok so i've passed richard the gerber files for a review, and i've done the replacement of all 10uF 0805 capacitors with twin 4.7uF 0603. full details outlined in a new update, which will likely be out next year.
i'm now in to "examining gerbers closely" mode which usually takes me 2-3 days, i go over them dozens of times, looking for things like "GND VIAs that have been removed by PADS" and "tracks that aren't separated by GND when they were previously" and "power lines and power planes that might not hold enough current" and so on.
it needs to be done several times as there's so much detail it's easy to miss things.
then when both richard and i are happy it'll go off to mike for him to order, that'll take about.... 3-6 weeks. there will be NO rushing here, they tend to screw it up. another set of 10 components will need to be ordered, and we get to make 10 more 2.7.5 PCBs.
this time the assembly will be .... complicated by the fact that we need to try out 1666mhz and 1800mhz DDR3 RAM ICs (which will be run at only 375mhz), because the 1033mhz DDR3 RAM is getting F*****G expensive, it's hit the tail-end of its lifecycle.
i might also have to ask him to track down some 1GB (4x 256mb) RAM ICs as a "just in case" as well.
l.
ok i'm done with the 0805 10uF capacitors, and mostly-done messing about looking at the gerber files for areas where ground tracks are missing. currently i've added a keepout area around the DDR3 lines because that's what i've seen done in other designs.
gotta get moving on this, richard - it'll be another 5-6 weeks if we miss the window of opportunity before chinese new year.
l.
On Jan 3, 2018, at 05:03, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok i'm done with the 0805 10uF capacitors, and mostly-done messing about looking at the gerber files for areas where ground tracks are missing. currently i've added a keepout area around the DDR3 lines because that's what i've seen done in other designs.
gotta get moving on this, richard - it'll be another 5-6 weeks if we miss the window of opportunity before chinese new year.
My initial feedback is it looks pretty nice. I sat down, read the documentation for the gerber viewer that comes with KiCAD and started getting my feet wet.
One recommendation for now as I have to leave for choir rehearsal--do the same thing with additional ground traces north and south of the ESD pads on layer 6 as you did on layer 1 to bring the distance between pad and ground down from 15mil to around the same as the pad-to-pad spacing of the ESD component pads.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Jan 4, 2018 at 12:22 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
My initial feedback is it looks pretty nice. I sat down, read the documentation for the gerber viewer that comes with KiCAD and started getting my feet wet.
good god. you read documentation?? :)
One recommendation for now as I have to leave for choir rehearsal--do the same thing with additional ground traces north and south of the ESD pads on layer 6 as you did on layer 1 to bring the distance between pad and ground down from 15mil to around the same as the pad-to-pad spacing of the ESD component pads.
yep sorted. will send you new gerber set, for anyone else to see (and also make it easier for you, richard) attached screenshot.
l.
On Wed, Jan 3, 2018 at 9:53 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Jan 4, 2018 at 12:22 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
My initial feedback is it looks pretty nice. I sat down, read the documentation for the gerber viewer that comes with KiCAD and started getting my feet wet.
good god. you read documentation?? :)
I scanned it fairly quickly to get a good idea of how to interact with the program. That way I had some idea what the icons meant and what functions were available in the user interface. (Okay, I've written documentation before so I figured since it was available I'd look it over. It gave me a pretty quick idea of how the user interactions are structured.)
One recommendation for now as I have to leave for choir rehearsal--do the same thing with additional ground traces north and south of the ESD pads on layer 6 as you did on layer 1 to bring the distance between pad and ground down from 15mil to around the same as the pad-to-pad spacing of the ESD component pads.
yep sorted. will send you new gerber set, for anyone else to see (and also make it easier for you, richard) attached screenshot.
Beautiful!
I think that was the most important change I noticed. I am mainly looking at the HDMI which we have been laboring over the last few months.
My next suggestion has an associated question:
I notice that north of the long east-west transmission line, at the northern keepout boundary on layer 6, there are a couple of vias that have almost complete ground shield between the vias and the HDMI TX2 pair.
Question: What is the fill polygon width for ground fill on layer 6?
I can see two fairly simple solutions to complete the ground shield around these vias: 1. Add traces to complete the ground shield between vias and HDMI differential pair. 2. Adjust trace/fill polygon width for ground fill on layer 6 till the ground shield is complete.
I'll sleep on it and take another look tomorrow morning.
On Wed, Jan 3, 2018 at 10:20 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
I notice that north of the long east-west transmission line, at the northern keepout boundary on layer 6, there are a couple of vias that have almost complete ground shield between the vias and the HDMI TX2 pair.
Question: What is the fill polygon width for ground fill on layer 6?
I can see two fairly simple solutions to complete the ground shield around these vias:
- Add traces to complete the ground shield between vias and HDMI
differential pair. 2. Adjust trace/fill polygon width for ground fill on layer 6 till the ground shield is complete.
I'll sleep on it and take another look tomorrow morning.
Looks like you already addressed this in the latest gerbers! Any chance we could use another trace to even up the little dimples that are left in the edge facing the differential pairs?
I glanced at parts of the rest of the board but it would be much more straightforward with the schematics. Do you have a way to compare changes with previous versions of the board to see if PADS did anything surprising behind your back?
Sincerely, Richard
On Fri, Jan 5, 2018 at 7:32 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Looks like you already addressed this in the latest gerbers!
yehyeh.
Any chance we could use another trace to even up the little dimples that are left in the edge facing the differential pairs?
always best to screenshot / arrow-mark it, richard. round-trip delays getting critical here, we're up to 5th january already. attached green arrows, i am guessing you mean, i remember you said that causes... something-or-other... capacitance-related?
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
I glanced at parts of the rest of the board but it would be much more straightforward with the schematics.
not so concerned about the rest of the board, it's mainly the HDMI. PDF version of schematics should be here http://hands.com/~lkcl/eoma/DS113-V2.7-2017-02-17.pdf
Do you have a way to compare changes with previous versions of the board to see if PADS did anything surprising behind your back?
the only way would be visual pdf diffs, and i've made several minor changes as well that would show up and need to be reviewed, one by one, and eliminated. i've found it's easier just to go over the board making minor tweaks, because each time i do so i find one more "little thing" such as a place where there's a capacitor that doesn't have a nearby GND via and so on.
On Fri, Jan 5, 2018 at 7:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
rectangular all-layers keepout, showing 1 and 3 here... damn layers 2 and 5 have a weird shape (not enough clearance auto-generated) let me make it an oval all-layers keepout instead...
will deal with the other end next.
l.
On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 7:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
rectangular all-layers keepout, showing 1 and 3 here... damn layers 2 and 5 have a weird shape (not enough clearance auto-generated) let me make it an oval all-layers keepout instead...
Those do look very nice, indeed!
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Jan 5, 2018 at 8:27 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 7:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
rectangular all-layers keepout, showing 1 and 3 here... damn layers 2 and 5 have a weird shape (not enough clearance auto-generated) let me make it an oval all-layers keepout instead...
Those do look very nice, indeed!
did the trick. pain doing them by hand, had to do the flood-fill, then adjust the keepout, then write down by hand the distances that the keepout fitted cleanly to the edges, _then_ throw that file away, _then_ go back and put the rectangle left-right... bletch :)
anyway i moved the PWM via up a bit, left the 3V3 VIAs where they were - sorted.
l.
On Fri, Jan 5, 2018 at 4:05 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 8:27 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
rectangular all-layers keepout, showing 1 and 3 here... damn layers 2 and 5 have a weird shape (not enough clearance auto-generated) let me make it an oval all-layers keepout instead...
Those do look very nice, indeed!
did the trick. pain doing them by hand, had to do the flood-fill, then adjust the keepout, then write down by hand the distances that the keepout fitted cleanly to the edges, _then_ throw that file away, _then_ go back and put the rectangle left-right... bletch :)
anyway i moved the PWM via up a bit, left the 3V3 VIAs where they were - sorted.
The results are great! Thanks for all the hard work to make it happen.
So I'm happy with the layout of the HDMI!
I checked for vias in component pads (manufacturability issue) and since the gerber viewer I'm using complains about all the tools in the drill file when I load it, I can't see the via holes. So there may be several false alarms in this list. Could even be mostly false alarms. But I would definitely check out C3 on layer 1 as there seems to be a via in the middle of one of the pads. (Marked with red arrow in attached picture.)
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Jan 5, 2018 at 4:02 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 4:05 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 8:27 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
rectangular all-layers keepout, showing 1 and 3 here... damn layers 2 and 5 have a weird shape (not enough clearance auto-generated) let me make it an oval all-layers keepout instead...
Those do look very nice, indeed!
did the trick. pain doing them by hand, had to do the flood-fill, then adjust the keepout, then write down by hand the distances that the keepout fitted cleanly to the edges, _then_ throw that file away, _then_ go back and put the rectangle left-right... bletch :)
anyway i moved the PWM via up a bit, left the 3V3 VIAs where they were - sorted.
The results are great! Thanks for all the hard work to make it happen.
yeah you too. dang it's been a while :)
So I'm happy with the layout of the HDMI!
aawesome
I checked for vias in component pads (manufacturability issue) and since the gerber viewer I'm using complains about all the tools in the drill file when I load it, I can't see the via holes. So there may be several false alarms in this list. Could even be mostly false alarms.
it's not. basically the trick has been, due to cramped space, to put at least 2 VIAs around power decoupling capacitors (not done by me), and they're just on the edge. space is pretty crowded and all previous boards worked fine (and there's been a *lot* of pre-production boards now).
But I would definitely check out C3 on layer 1 as there seems to be a via in the middle of one of the pads. (Marked with red arrow in attached picture.)
yehyeh good call that one was me, i had to reorganise the nearby (East) power capacitors, and shuffle (West) the components next door, in order to fit two (horizontal) 0603 4.7uF where there was previously one (vertical) 0805 10uF.
shuffled that VIA up as there's plenty of space.
iiii think we're good.
now the only concern is, blasted frickin apple, has sucked world-wide demand not just for the entire supply of 0.1 10 and 100uF capacitors but f*****g DDR3 and eMMC *as well*.
i now have to be extremely careful on selecting the right DDR3 RAM ICs... *sigh*.
l.
ok gerbers sent. waiting for confirmation from mike. with DDR3 prices being insane i'm not going to push hard for the PCB to be made, nor the assembly done in a hurry.
l.
On Jan 5, 2018, at 22:37, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok gerbers sent. waiting for confirmation from mike.
Cheers!
with DDR3 prices being insane i'm not going to push hard for the PCB to be made, nor the assembly done in a hurry.
Not having a rush on PCB fabrication or assembly may help control costs. Do you see DDR3 prices relaxing after Chinese New Year?
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Jan 6, 2018 at 6:45 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Jan 5, 2018, at 22:37, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok gerbers sent. waiting for confirmation from mike.
Cheers!
with DDR3 prices being insane i'm not going to push hard for the PCB to be made, nor the assembly done in a hurry.
Not having a rush on PCB fabrication or assembly may help control costs. Do you see DDR3 prices relaxing after Chinese New Year?
absolutely no idea, and no way to tell.
l.
On Jan 5, 2018, at 21:50, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 4:02 PM, Richard Wilbur richard.wilbur@gmail.com wrote: On Fri, Jan 5, 2018 at 4:05 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 8:27 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
it's not. basically the trick has been, due to cramped space, to put at least 2 VIAs around power decoupling capacitors (not done by me), and they're just on the edge. space is pretty crowded and all previous boards worked fine (and there's been a *lot* of pre-production boards now).
In that case, no problem.
But I would definitely check out C3 on layer 1 as there seems to be a via in the middle of one of the pads. (Marked with red arrow in attached picture.)
yehyeh good call that one was me, i had to reorganise the nearby (East) power capacitors, and shuffle (West) the components next door, in order to fit two (horizontal) 0603 4.7uF where there was previously one (vertical) 0805 10uF.
shuffled that VIA up as there's plenty of space.
iiii think we're good.
Well I'm glad I looked and you had chance to fix it!
now the only concern is, blasted frickin apple, has sucked world-wide demand not just for the entire supply of 0.1 10 and 100uF capacitors but f*****g DDR3 and eMMC *as well*.
i now have to be extremely careful on selecting the right DDR3 RAM ICs... *sigh*.
So the situation is the chips at the speed you designed for are much more expensive while faster ones are cheaper? So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for?
On Sat, Jan 6, 2018 at 6:35 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
now the only concern is, blasted frickin apple, has sucked world-wide demand not just for the entire supply of 0.1 10 and 100uF capacitors but f*****g DDR3 and eMMC *as well*.
i now have to be extremely careful on selecting the right DDR3 RAM ICs... *sigh*.
So the situation is the chips at the speed you designed for are much more expensive while faster ones are cheaper?
yyup... except it's more complicated than that: insatiable demand for fulfilling apple apple apple apple apple apple orders is driving EVERYTHING up as there is only a fixed capacity at the foundries making DDR RAM. consequently, all remaining DDR RAM ICs at *ALL* capacities and sizes are falling behind... consequently prices are spiralling out of control.
So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for?
yyup. have to use the 1800mhz 1.5v x8 DDR3 IC, which fortunately happens to be down-compatible with 667mhz. the 1.35v DDR3L variant of the same chip is *not*.
still, i cannot risk just relying on one possible DDR3 IC, so i will have to source 1600mhz as well... and also last resort a 2gigabit IC which will total, qty 4, only 1GBYTE of RAM.
the budget's fixed... it's just the way it's going to have to be. make adjustments that fit within the budget, end of story.
l.
On Jan 5, 2018, at 23:49, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Jan 6, 2018 at 6:35 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for?
yyup. have to use the 1800mhz 1.5v x8 DDR3 IC, which fortunately happens to be down-compatible with 667mhz. the 1.35v DDR3L variant of the same chip is *not*.
Your changes to the power supply capacitors and vias should help accommodate faster edges, etc. from the faster chips.
still, i cannot risk just relying on one possible DDR3 IC, so i will have to source 1600mhz as well... and also last resort a 2gigabit IC which will total, qty 4, only 1GBYTE of RAM.
the budget's fixed... it's just the way it's going to have to be. make adjustments that fit within the budget, end of story.
Here's hoping the faster ones fit the budget and the circuit as I'm a big fan of providing as much RAM as possible!
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Jan 6, 2018 at 7:12 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
yyup. have to use the 1800mhz 1.5v x8 DDR3 IC, which fortunately happens to be down-compatible with 667mhz. the 1.35v DDR3L variant of the same chip is *not*.
Your changes to the power supply capacitors and vias should help accommodate faster edges, etc. from the faster chips.
yehyeh. not sure if the A20 can handle faster, but we'll see what happens. some people have managed 450mhz i think.
l.
On Jan 5, 2018, at 23:49, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Jan 6, 2018 at 6:35 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for?
yyup. have to use the 1800mhz 1.5v x8 DDR3 IC, which fortunately happens to be down-compatible with 667mhz. the 1.35v DDR3L variant of the same chip is *not*.
I was doing a little reading about DDR3 and noticed the 1.35V DDR3L memory chips are happy talking/running with 1.5V DDR3 systems.[1] So are you saying the 1800mhz 1.35v x8 DDR3L IC is not happy running at 667MHz? (Clock rate incompatibility versus voltage incompatibility?)
References: [1] https://en.m.wikipedia.org/wiki/DDR3_SDRAM
=On Sat, Jan 6, 2018 at 2:28 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Jan 5, 2018, at 23:49, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Jan 6, 2018 at 6:35 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for?
yyup. have to use the 1800mhz 1.5v x8 DDR3 IC, which fortunately happens to be down-compatible with 667mhz. the 1.35v DDR3L variant of the same chip is *not*.
I was doing a little reading about DDR3 and noticed the 1.35V DDR3L memory chips are happy talking/running with 1.5V DDR3 systems.[1] So are you saying the 1800mhz 1.35v x8 DDR3L IC is not happy running at 667MHz? (Clock rate incompatibility versus voltage incompatibility?)
correct. the 1800mhz hynix 1.35v is specifically cut off from supporting 667mhz and 800mhz modes. this boards' DDR3 layout is... not... exactly... great... but it works, as long as you don't go over 350mhz.
funnily enough that turns out to be absolutely fine because four DDR3x8 ICs running at 350mhz is abouuut.... half a watt or thereabouts. power consumption goes up on a square law so it would be really bad to run much faster, even if it was possible.
l.
still doing these tiny little changes, it's just the way it goes: every time you look at the board in close zoom, it's like... "hmmm, yeah that could be improved" and this latest one, it's the (now pair of) capacitors for the main DDR3 power stabilisation.
previously this was a single 0805 capacitor lined up vertically. there was plenty of connecting VIAs down to layer 4 DDR3 1.5v power plane.... but because there were a MASSIVE array of tracks underneath the GND pads there were no GND vias. whoops. and when replacing with two 0603 4.7uF capacitors, i maintained that mistake.
i decided to turn both 0603 capacitors horizontal and then to beef up the number of GND vias. this has the unintended side-effect of drilling quite a lot of holes into the layer 4 DDR3 1.5v power plane however as the GND vias are at the edge of the plane i consider this acceptable. i have however made sure that the plane is free of holes for getting the actual 1.5v power *in* to the plane, if that makes any sense.
anyway a few more things like this... richard if you're happy with the beginning of the HDMI area i'll send the gerbers off straight away.
l.
On Jan 5, 2018, at 21:28, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
still doing these tiny little changes, it's just the way it goes: every time you look at the board in close zoom, it's like... "hmmm, yeah that could be improved" and this latest one, it's the (now pair of) capacitors for the main DDR3 power stabilisation.
previously this was a single 0805 capacitor lined up vertically. there was plenty of connecting VIAs down to layer 4 DDR3 1.5v power plane.... but because there were a MASSIVE array of tracks underneath the GND pads there were no GND vias. whoops. and when replacing with two 0603 4.7uF capacitors, i maintained that mistake.
i decided to turn both 0603 capacitors horizontal and then to beef up the number of GND vias. this has the unintended side-effect of drilling quite a lot of holes into the layer 4 DDR3 1.5v power plane however as the GND vias are at the edge of the plane i consider this acceptable. i have however made sure that the plane is free of holes for getting the actual 1.5v power *in* to the plane, if that makes any sense.
Good stuff. Should make the power supply more stable for the DDR3 RAM chips!
anyway a few more things like this... richardt if you're happy with the beginning of the HDMI area i'll send the gerbers off straight away.
I am happy with the HDMI but I was going to ask about silkscreen on pads--I saw several instances of silkscreen on areas you'll want covered in solder. Sorry I didn't bring it up earlier. Not a problem if you aren't having the silkscreen printed. Your board fab may also do the right thing and move the offending notations.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Jan 6, 2018 at 6:24 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I am happy with the HDMI but I was going to ask about silkscreen on pads--I saw several instances of silkscreen on areas you'll want covered in solder. Sorry I didn't bring it up earlier. Not a problem if you aren't having the silkscreen printed. Your board fab may also do the right thing and move the offending notations.
they do. they exclude silkscreen from solder mask areas.
l.
On Jan 5, 2018, at 23:27, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Sat, Jan 6, 2018 at 6:24 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
I am happy with the HDMI but I was going to ask about silkscreen on pads--I saw several instances of silkscreen on areas you'll want covered in solder. Sorry I didn't bring it up earlier. Not a problem if you aren't having the silkscreen printed. Your board fab may also do the right thing and move the offending notations.
they do. they exclude silkscreen from solder mask areas.
Wonderful! One less problem to worry about.
On Fri, Jan 5, 2018 at 12:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 7:32 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Any chance we could use another trace to even up the little dimples that are left in the edge facing the differential pairs?
always best to screenshot / arrow-mark it, richard. round-trip delays getting critical here, we're up to 5th january already.
I have attached a screenshot with red arrows. It is taken from the long straight differential microstrip transmission lines on layer 6. These are otherwise so clean and straight.
attached green arrows, i am guessing you mean, i remember you said that causes... something-or-other... capacitance-related?
The ones you marked weren't the ones I was looking at. I think they are probably fine as they aren't too sharp, they mind the 15mil clearance, and we are turning 90 degrees out of some signal vias onto the top of the board. (If they were pointing at a straight side I'd be more worried.)
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
It is kind of tumultuous with the pairs coming from close quarters on layer 1 and still to be sorted through the intra-pair skew-compensating wiggles. What you've done at that end looks much better.
I glanced at parts of the rest of the board but it would be much more straightforward with the schematics.
not so concerned about the rest of the board, it's mainly the HDMI. PDF version of schematics should be here http://hands.com/~lkcl/eoma/DS113-V2.7-2017-02-17.pdf
I'll concentrate on the HDMI, then.
Do you have a way to compare changes with previous versions of the board to see if PADS did anything surprising behind your back?
the only way would be visual pdf diffs, and i've made several minor changes as well that would show up and need to be reviewed, one by one, and eliminated. i've found it's easier just to go over the board making minor tweaks, because each time i do so i find one more "little thing" such as a place where there's a capacitor that doesn't have a nearby GND via and so on.
Sounds good.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Jan 5, 2018 at 8:25 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Fri, Jan 5, 2018 at 12:44 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Jan 5, 2018 at 7:32 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Any chance we could use another trace to even up the little dimples that are left in the edge facing the differential pairs?
always best to screenshot / arrow-mark it, richard. round-trip delays getting critical here, we're up to 5th january already.
I have attached a screenshot with red arrows. It is taken from the long straight differential microstrip transmission lines on layer 6. These are otherwise so clean and straight.
gooot it. yehyeh there's signals (3V3) and stuff close by (unavoidably), and i have to put manual GND tracks in because the flood-fill won't blotch in to spaces narrower than 10mil... it's a setting somewhere and i kinda prefer it that way, otherwise flood-fill tends to get into some really small spaces and creates awkward-looking tiny shapes.
attached green arrows, i am guessing you mean, i remember you said that causes... something-or-other... capacitance-related?
The ones you marked weren't the ones I was looking at. I think they are probably fine as they aren't too sharp, they mind the 15mil clearance, and we are turning 90 degrees out of some signal vias onto the top of the board. (If they were pointing at a straight side I'd be more worried.)
with you.
there's a few more like that back at the source diff-pair vias, i'll think about whether to drop a plain square keepout in place (to preserve 15mil) or a straight manual track. track would cut clearance to around 12mil. thoughts?
It is kind of tumultuous with the pairs coming from close quarters on layer 1 and still to be sorted through the intra-pair skew-compensating wiggles. What you've done at that end looks much better.
yay :)
I glanced at parts of the rest of the board but it would be much more straightforward with the schematics.
not so concerned about the rest of the board, it's mainly the HDMI. PDF version of schematics should be here http://hands.com/~lkcl/eoma/DS113-V2.7-2017-02-17.pdf
I'll concentrate on the HDMI, then.
yes please
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Dec 22, 2017 at 9:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Dec 22, 2017, at 07:51, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Dec 22, 2017 at 8:54 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
[…]
this is a pain! i might see if i can set a clearance to GND on individual tracks / connections as opposed to NETs.
ok that worked. just uploading a video here:
turns out that there's a feature i'd not used before, called "conditional rules". you can specify that *if* GND meets HDMI Group, clearance rules shall be different. ordinarily you have to forcibly set the *entire* GND plane to specific clearances (to ALL objects), or the *entire* HDMI group to specific clearances (to ALL objects)... this "conditional" rule does the trick.
Nice work! That certainly simplifies things!
tell me about it. and also makes for much cleaner / accurate separation.
I believe that the right thing is to not extend the layer 5 ground keepout under the differential nets on their way out to the connector because it is the ground plane for layer 6.
that makes sense.
The reason for dropping the ground plane under the connector pins (layer 1) from layer 2 to layer 5 is that the pins are so close to each other.
yyeahhh but so are the pins on the bottom layer ESD... which are covered by the layer 5 GND keepout hole... it was under the connector i was concerned about, with the VIAs on pins 4 10 and 16 (right-hand row of 9) being guard VIAs that are within 5mil of HTX1P/N and THXCP/N...
But we are still interested in the shielding effect of ground plane below the high-frequency signals (on the differential pairs) on layer 1 and between the signals on layer 1 and those sneaking under on layer 6.
yehyeh.
That's my reason for keeping layer 5 ground fill everywhere except under the layer 6 high-frequency pads of the ESD (where he drop to ground on layer 4).
yehyeh, with you.
l.
On Dec 22, 2017, at 20:22, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Dec 22, 2017 at 9:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The reason for dropping the ground plane under the connector pins (layer 1) from layer 2 to layer 5 is that the pins are so close to each other.
yyeahhh but so are the pins on the bottom layer ESD... which are covered by the layer 5 GND keepout hole... it was under the connector i was concerned about, with the VIAs on pins 4 10 and 16 (right-hand row of 9) being guard VIAs that are within 5mil of HTX1P/N and THXCP/N...
Those ground vias I'm not so worried about as they don't look so much different to the proximity of neighbouring connector pins.
On Sat, Dec 23, 2017 at 4:13 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Those ground vias I'm not so worried about as they don't look so much different to the proximity of neighbouring connector pins.
ok. awesome.
On Tue, Dec 5, 2017 at 5:41 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Reflections are more troublesome the further you get from the
signal source. Close to the source the reflection arrives at the source during the signal rise time and can be overcome by the line driver.
Deviations from path in due NorthEast direction (+ signifies change in the NorthWest direction, - signifies change in the SouthEast direction, units in mil) <step> <Northern keepout> <TX1> <TX0> <TXC> <Southern keepout> 0 0 0 0 0 0
[...]
8 -1 1 2 3 4
okaay so the idea is, just after the long straight you make a series of very tiny corrections by bringing each of the tracks inwards - closer together - so that when you get to the point where you *have* to be 5-7mil apart you're already neeearrrrly that far apart *anyway* so it's not so bad.
That's the basic idea.
I spent a little time reflecting on the big picture (terrible pun, I know): differential driver -> connected to PCB with small clearances for the first ~100mil -> via from layer 1 to layer 6, sort out intra-pair skew ~100mil? -> differential microstrip transmission line (111 Ohm characteristic impedance) ~500mil? -> ESD suppression and sort out connections to cable connector ~200mil -> 100 Ohm cable connector -> 100 Ohm cable ~10000mil -> 100 Ohm cable connector -> 100 Ohm PCB connection to -> 100 Ohm HDMI receiver.
Many impedance improprieties can be forgiven during the signal rise time--which is to say within the distance the signal propagates during the first quarter wavelength of its highest characteristic frequency. In this case we already calculated that to be 4300mil, which looks like it will get us safely on to the cable!
In pondering the big picture I was reminded that the impedance on the cable is again 100 Ohm, so unless we had a chance to taper back out to that we will create a bigger impedance issue at the connector (having tapered down to smaller clearances over ~100mil and then keeping those clearances for another ~200mil out to the connector) than the short problems of the incursions into our design parameters for the differential microstrip transmission line. The ESD and connector lands represent pretty short distances in the direction of signal propagation. Their are other traces and vias that come closer but over a relatively very short distance in the direction of signal propagation. (We can combat the small problems at component lands by possibly removing the ground plane directly below--essentially moving it lower using a different layer for ground plane. Maybe use layer 3 or 4 instead of 2 or 5?)
So, if we had to adapt a line driver with some impedance to a line of different impedance, the taper would be a fine solution. We, on the other hand, have 100 Ohm impedance on both sides of the problem area and thus are better served leaving the conduction path at 100 Ohm impedance and taking some small hits rather than changing it without the room to do as good a job of changing it back.
Sorry for jumping down that rabbit hole! The solution was worse than the problem! That's what I get for focusing too closely on details without gazing at the forest again, once in a while.
Sincerely, Richard
hiya richard,
ok so just to check, are you recommending a multi-staggered approach, according to that table: 0 0 0 0 0 0 1 -1 1 2 3 4 2 -1 1 2 3 4 3 -1 1 2 3 4 4 -2 2 4 6 8 5 -2 2 4 6 8 6 -1 1 2 3 4 7 -1 1 2 3 4 8 -1 1 2 3 4
so that would be *eight* separate bring-ins?
or are you just recommending the *one* bring-in, where the table specifies how *much* each particular trace should be offset by? so 0 would be dummy, 1 would be TX2N, 2 would be TX2P .... 8 would be TX2P?
(bear in mind, like i mentioned, i am thinking of keeping TX1 where it is instead of TX2, because of the diff-pair VIA positions, i can adjust the offsets accordingly)
l.
On Sat, Dec 9, 2017 at 12:39 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok so just to check, are you recommending a multi-staggered approach, according to that table: 0 0 0 0 0 0 1 -1 1 2 3 4
[...]
8 -1 1 2 3 4
so that would be *eight* separate bring-ins?
Yes, 8 separate, small steps bringing the pairs closer.
or are you just recommending the *one* bring-in, where the table specifies how *much* each particular trace should be offset by?
You are missing the heading that specified: <step #> <north keepout> <TX1> <TX0> <TXC> <south keepout>
(bear in mind, like i mentioned, i am thinking of keeping TX1 where it is instead of TX2, because of the diff-pair VIA positions, i can adjust the offsets accordingly)
That would be fine to hold TX1 stationary instead of TX2, it even makes for a more symmetric taper thus the maximum offset will be smaller. <step#> <north keepout> <TX2> <TX0> <TXC> <south keepout> 0 0 0 0 0 0 1 -2 -1 1 2 3 2 -2 -1 1 2 3 3 -2 -1 1 2 3 4 -4 -2 2 4 6 5 -4 -2 2 4 6 6 -2 -1 1 2 3 7 -2 -1 1 2 3 8 -2 -1 1 2 3
P.S. See other post where I climbed out of the rabbit hole and recommend against doing the taper after all.
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Good grief that took awhile! I'm now completely sold on the concept of Computer-Aided Design (I've used some awkward implementations before but this was done with pencil, pen, measuring tape, and book spine for straight edge).
... what... you don't just draw them by hand? :)
rright. there's no way i'm doing this layout by hand. i'm going to do something that i meant to do a long time ago: investigate how to use the DCOM interface to PADS. that *shudder* means installing python2.7 under windows.
basically it should be perfectly possible to use the COM interface to hunt down the tracks by name, and in an *automated* fashion add in track segments according to the layout you designed, richard.
what that also means is, if i get it wrong, it's a simple matter of adjusting the python program to redo it.
ohh dearie me :)
l.
ok i looked at using the COM interface, and... it's incomplete, lacking the set of required functions to do things such as "add track".
sooOoo... i think i'll take a different approach: i'll write a parser for the ASCII-exported version of the PCB file, track down the relevant sections and replace them with auto-generated tracks.
actually what this approach would allow is, to potentially add in proper curves. if i'm going to use tables mathematically to automate the track generation, i might as well go the whole hog, richard, and do the equations from that 1956 paper, properly. even if it means adding thousands of segments.
what do you think?
l.
On Sun, Dec 10, 2017 at 4:19 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok i looked at using the COM interface, and... it's incomplete, lacking the set of required functions to do things such as "add track".
sooOoo... i think i'll take a different approach: i'll write a parser for the ASCII-exported version of the PCB file, track down the relevant sections and replace them with auto-generated tracks.
actually what this approach would allow is, to potentially add in proper curves. if i'm going to use tables mathematically to automate the track generation, i might as well go the whole hog, richard, and do the equations from that 1956 paper, properly. even if it means adding thousands of segments.
what do you think?
Sounds pretty cool! How about we revisit this when we implement something that uses a microwave radio (cellular radio, wifi, etc.)?
On Sat, Dec 9, 2017 at 9:37 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Tue, Dec 5, 2017 at 12:30 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
Good grief that took awhile! I'm now completely sold on the concept of Computer-Aided Design (I've used some awkward implementations before but this was done with pencil, pen, measuring tape, and book spine for straight edge).
... what... you don't just draw them by hand? :)
rright. there's no way i'm doing this layout by hand.
God forbid! I had no intention of recommending anyone do the layout by hand. I was doing part of it that way and lamenting the inconvenience.
i'm going to do something that i meant to do a long time ago: investigate how to use the DCOM interface to PADS. that *shudder* means installing python2.7 under windows.
basically it should be perfectly possible to use the COM interface to hunt down the tracks by name, and in an *automated* fashion add in track segments according to the layout you designed, richard.
what that also means is, if i get it wrong, it's a simple matter of adjusting the python program to redo it.
ohh dearie me :)
Sounds pretty cool--like a plugin interface for PADS?
arm-netbook@lists.phcomp.co.uk
-
Luke Kenneth Casson Leighton -
mike.valk＠gmail.com -
Richard Wilbur