On Mon, Nov 20, 2017 at 11:12 PM, zap calmstorm@posteo.de wrote:

I am surprised I thought you would want the c class?

that's industrial.

Do you think the m class will be lightweight enough for your purposes?

it's the "mobile" class. get this: in 28nm they're looking at 600mW power consumption for the m-class :)

l.

--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Nov 21, 2017 at 9:47 AM, Bill Kontos vkontogpls@gmail.com wrote:

600mW sound like an aweful little for desktop use. I can't fathom javascript loading speeds in such a package. For reference my phone has a 3 watt chip( lg g3, snapdragon 801, 28nm) and I do notice some lag with webpages. Now granted the high rez screen (1440 x 2560) doesn't help but 600mW vs 3 W looks like a big drop.

RISC-V is *significantly* less power-hungry, performance/watt. also, those 3 watts will include a Monster GPU, which will be being used for accelerated graphics. and, there will be *two* 32-bit data-wide DDR3 interfaces, not the one. that'll be 600mW minus the interfaces btw (including DDR3 driving and GPIO).

l.

On Tue, Nov 21, 2017 at 10:15 AM, Bill Kontos vkontogpls@gmail.com wrote:

The A72 which they quote as their target is consuming 700-900 watts per core, let alone the entire package. If they can drop power consumption that much( assuming a quad core ~75% less power consumption) then this is way more revolutionary than I thought.

there's a paper comparing the two in 45nm, and yes RISC-V was around half the power.

Does that cover all the specialized hardware and video accel too?.

no.

What's your definition of a monster gpu?

MALI T650 or so (whatever it is). not MALI-400, that's "little monster" :)

Running 1080p at 60hz on a browser is a must imo and wether we like it or not wayland is the future so it will also need some sort of opengl compliant gpu just for futureproofing.

the initial plan is to use the main processor with some basic SIMD vector-processing instructions, which in quad-core would be more than adequate.

bear in mind this is - preliminarily - to be around a USD $3 SoC with between 320 and 400 pins.

l.

--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Nov 21, 2017 at 11:44 AM, Bill Kontos vkontogpls@gmail.com wrote:

On Tue, Nov 21, 2017 at 12:23 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:

...

the initial plan is to use the main processor with some basic SIMD vector-processing instructions, which in quad-core would be more than adequate.

bear in mind this is - preliminarily - to be around a USD $3 SoC with between 320 and 400 pins.

Alright that makes sense. Thanks for your time explaining it to me.

wheww, no deliberate mistakes spotted... :)

http://rhombus-tech.net/riscv/shakti/m_class/ http://rhombus-tech.net/riscv/shakti/m_class/pinouts/ http://rhombus-tech.net/riscv/shakti/m_class/pinouts.py

l.

On Tue, Nov 21, 2017 at 11:23 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:

https://pdfs.semanticscholar.org/f6d5/e754da444b7ede6e4eeaf0d61e8cbb82ade9.p...

https://arxiv.org/abs/1607.02318

so, the compression and something called macro-op fusion results in a significant reduction in code size that happens also to result in less cache usage and also faster execution time. how about that, huh? :)

Yes that was the entire point of risc-v, to make a risc isa with what we learned from the mistakes of the past( there is a video going in depth on the risc-v youtube channel about instruction density that I can't seem to locate right now, but anyway removing the extra step x86-64 has makes perfect sense). Although from your second link the snapdragon 801 example that I gave before is supposed to be slightly denser or equal to the compressed version of risc v, so this alone doesn't seem to explain the difference. Anyway, if those are their targets we'll have to wait and see what they come up with.

http://rhombus-tech.net/riscv/shakti/m_class/pinouts/

added the smartphone/tablet scenario, added DDR3, SYS and POWER pins.... total comes to 290! that's around 18x18 on a side, maybe 19x19 to make space for routing, which in a BGA form-factor @ 0.8mm pitch would be a 15x15mm package!

0.8mm deliberately because it's far, far easier to do a PCB with larger vias, and you can (i think) just about get a 4mil maybe even a 5mil trace in between 0.8mm BGA pads.

cooool :)

l.