[Arm-netbook] EOMA68 Computing Devices Update: Measurements and a Hypothesis

Paul Boddie paul at boddie.org.uk
Fri Jan 24 15:22:49 GMT 2020


Sorry, just warming this thread up with a few random observations...

On Monday 2. December 2019 20.05.55 Luke Kenneth Casson Leighton wrote:
> On Mon, Dec 2, 2019 at 3:23 PM Paul Boddie <paul at boddie.org.uk> wrote:
> > 
> > https://www.crowdsupply.com/eoma68/micro-desktop/updates/measurements-and-> > a-hypothesis
> > 
> > From what it says, it rather sounds like same (or a similar) problem is
> > being encountered as the one which happened with the Ingenic JZ4775
> > boards:
> yehyeh.  except i didn't know about the PCBs not actually matching the
> gerber files, back then.

OK, that would have been a bit awkward for troubleshooting, too.


> i did actually partly get them up and running, but i'd put a 24mhz XTAL on
> instead of 48mhz, and the SD/MMC wasn't having it.  i tried fixing that in
> software (doubling the PLL frequencies for the SD/MMC) but couldn't get it
> up and running.

Yes, I imagine that the external oscillator is supposed to be 48MHz, and there 
may well be a limit to how far you can get (and how well it will work) by just 
using the PLL multipliers to get you to the frequencies you want.

> with it only being single-core 1ghz MIPS32 i dropped the investigation.

Interestingly, these SoCs all have other cores tucked away inside them, 
although you probably can't get away with regarding them as "proper" cores. 
For instance, on the JZ4780 (which is dual-core), but also the JZ4770, JZ4760 
and most likely the JZ4775, there's a core called AUX in the VPU and another 
one called MCU in the programmable DMA peripheral, both of them being XBurst 
cores but without certain amenities. Typically, they lack full MMUs, cache, 
FPUs and other things, but they seem to have fast access to some cache-like 
memory (TCSM).

I imagine that with a bit more investigation, other cores will pop up, but it 
is interesting how they get a lot of mileage out of the same architecture 
instead of mixing and matching (like the ARC cores in Intel CPUs or the 
OpenRISC cores in Allwinner SoCs). I was also trying to find out a bit more 
about the dedicated video and "vector matrix arithmetic" blocks associated 
with the VPU functionality, and one has to wonder what is going on there as 

Meanwhile, I wonder if you have heard from Mike lately or whether things are 
generally stalled with regard to the production issues. I guess that there 
will be a few weeks of holiday and disruption to take into account now, but I 
thought that maybe you'd caught up with him before the break.

Anyway, hope things are working out wherever you might be. (And that also goes 
for other readers of the list, of course!)


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