[Arm-netbook] OT: Food for thought

[Luke Kenneth Casson Leighton]

On Saturday, July 6, 2019, David Niklas <doark at mail.com> wrote:

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> Dear luke, list,
>
> As both luke and I are interested in chip fabrication I'm dropping this
> email with a link to a story on a SW tool that is designed to help
> improve designs based on how exactly a foundries process works.
>
> Luke, the wording in this article looks very carefully chosen in places.
> I'm totally in the dark as to why; e.g. "...the platform that analyzes
> yields enables secure collaboration between the foundry and customer."


The Foundries absolutely flatly refuse to trust their customers.

They flatly refuse to provide them with the "cells" for even basic things
like "a transiator".

So the tools basically have to create a GDS file with "holes" in them,
where things like "transistor" or "memory cell" or "IO Pad" go.

The fuckers won't even give information about the *size* of those "holes",
or how to connect to them, without an NDA.

However from what that article is *not* saying, even the "usual" NDA method
is just not enough, at the lower geometries. For 20nm and bigger, things
like MOSIS "rules" are perfectly sufficient. Lay out a design, no really
special knowledge that hasn't been known (realistically) for 20+ years, no
problem.

10nm and below is a WHOLE new level of weird.

It looks like there are some quantum interferences as well as EM and RF
issues, *and* probably some power and layout issues in the tinier
geometries, all of which the Foundries absolutely do not want the customers
to know about, because it constitues "reverse engineerable knowledge" about
how the Foundry lays out the chips, and a competitor Foundry could get hold
of that and start their own multi billion dollar money spinner.

So they did a deal with Synopsis, where they would tell *them* how to avoid
those pitfalls, as long as Synopsis promised to hide the information in
such a way that, whilst the customer got the layout advice they need to get
a working ASIC, they would in no way be able to know *how* that ASIC
actually got manufactured.

This is of course all inferred guesswork. Welcome to my world of low
probability logical deduction aka reverse engineering.

Bottom line is, we're literally decades and hundreds of millions of dollars
away from libre foundries.  I am probably out on those estimates by 1 to 2
orders of magnitude.  Luckily, DARPA recognises the problem and put up USD
150m to create fully libre automated ASIC layout software. It's a start.

In the meantime I am tracking what lip6.fr are doing (the team behind
alliance / coriolis2). They will be doing a 40nm tapeout using FreePDK,
ported to their cell library system.

Once successful it will be possible to follow in their footsteps and do a
40nm Libre RISCV tapeout.

The layout software produces *linearly* scaleable designs, so
hypothetically, as long as RF EM is ok (on chip) scaling to 28nm should be
feasible.  Just not straight away.

L.



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