[Arm-netbook] Linux now boots on 22nm RISC-V Shakti CPU

[Luke Kenneth Casson Leighton]

On Monday, July 30, 2018, Bill Kontos <vkontogpls at gmail.com> wrote:

> I've read somewhere that this requires specifically compiled binaries
> to work because it lacks some instructions. Is that correct?


>
Compressed, the 16 bit alternative representations for certain common
instructions, yes.

UCB ASSUMED that ALL systems running linux would automatically have these
because of COURSE it is optimal in ALL circumstances, without fucking well
consulting anyone outside of their elite clique / cartel, as to whether
this was actually the case.

 Hint: For VLIW its actually much easier and better to keep to regular
32bit, because of the branch prediction, and just absolutely go mental on
the memory bus bandwidth.

Prior to UCBs interference both Fedora and Debian had been compiled as
RV64IMAFD ie without compressed, which would easily have permitted
multiarch to have dual C and nonC binaries and libraries installed.

Now there will need to be a fork of both debian and fedora created, exactly
as the RISCV foundation CLAIMED that they were working to avoid happening
by "learning from the mistakes of the past"

rriiiight...


 If so
> will this limitation carry forward to other designs from the team?


If they implement C it will be fine.

 The primary thing is that demand for sovereign processors is so high from
various India Govt departments that they are overwhelmed with the rote task
of integrating peripherals onto AXI4 buses.  So i have spent the past 10
days urgently focussed on writing an autogenerator which creates the HDL
source code including the fabric and bus architecture, from a formal spec
in about 0.25 seconds flat.

Now the team will be free to work on much more strategic research like VLIW
xBitManip SIMD 3D graphics Vectors and Compressed and a more efficient RV16
encoding that will produce far more compact code than Compressed can.

Also it turns out that one of the students is doing a phd into fabric
autogeneration and optimisation. He was by a fantastic coincidence missing
the tool that would actually generate the code so that it could be properly
tested and synthesised.

Professor Kamakoti wrote all of Intel's formal verification test suites
when he used to work for them, and he is a big fan of dynamic
reconfigureable fabrics to suit different workloads.
Its the RISE lab. Reconfigurable something.

Its gonna get really really interesting. They have over 20 people on the
core team and they get like 20 to 30 interns helping over the summer for 6
months. Oh and me, skating around the campus, feeding the monkeys, farting
and using um colourful language shall we say, and writing python that spits
out BSV like it was born to Rock.

This is not a small operation, its set to completely steamroller ARM, Intel
and the RISCV Foundation itself if they dont wake up. All entirely libre
licensed and developed along informal IETF / ASF lines not a private club
/clique / cartel.

L.


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