[Arm-netbook] Microdesktop v1.7
richard.wilbur at gmail.com
Wed Jul 18 01:42:51 BST 2018
On Tue, Jul 17, 2018 at 7:02 AM, Pičugins Arsenijs <crimier at yandex.ru>
> Some thoughts:
> > 3. Add another SY6280 current limiter for +5V and connect to VGA pin
> > 9 (VESA power). Seems to be some difference of opinion on current
> > requirements: 50mA, 300mA-1000mA. If we were to limit at
> > 300mA, it should easily supply the needs of I2C serial EEPROM and
> > probably not over-tax our power supply.
> I've also seen the VGA/HDMI +5V used to power various converters
> (most often, HDMI->VGA, but I imagine the inverse is sometimes used
> as well).
I agree. I designed a converter that was powered by VGA DDC pin 9 power
or, in the absence of that, the VESA DDC SDA and SCL pull-up, or the VGA
horizontal and vertical synchronization signals. I don't remember exactly
how much power it used but it was relatively efficient as I used low-power
CMOS PAL (Programmable Array Logic, precursor to FPGA's). Basically its
largest-current operating mode was driving to TTL loads across the video
> > For VESA_SDA and VESA_SCL, add diode limiters connected to ground
> > similar to ESD117-ESD123 on the SD bus lines provided the
> > diode-limiting voltage is greater than VREFTTL nominal range.
> > Otherwise use BAT54S connected between ground and VREFTTL.
> Is it not possible that VESA_SDA and VESA_SCL are 5V? If so, they could
> require level shifting from 5V, am I wrong here?
It turns out VESA DDC uses I2C signalling. I2C signalling is
bi-directional open drain or open collector so the high state is due to a
pull-up resistor. The I2C bus voltage can be +5 V or +3.3 V, although
other voltages are permitted. All the devices on the bus have to
tolerate the bus voltage.
In my experience, the VESA DDC reference design used a pull-up supply of +5
V. The EOMA68 card doesn't have to drive it that high, simply go hi-Z and
the pull-up resistor in the microdesktop will pull it that high. But the
EOMA68 card will have to tolerate +5 V on those two lines (VESA_SDA,
VESA_SCL) or we jump into the tricky area of logic-level translation for
bi-directional open-drain signals.
Good observations. Thanks Arsenijs!
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