[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Richard Wilbur]

On Sep 22, 2017, at 04:17, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On Fri, Sep 22, 2017 at 8:51 AM, Richard Wilbur
> <richard.wilbur at gmail.com> wrote:
>> On Wed, Sep 20, 2017 at 4:22 PM, Luke Kenneth Casson Leighton
>> <lkcl at lkcl.net> wrote:
>>> On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur
>>> <richard.wilbur at gmail.com> wrote:
[…]
> i've not put in an HDMI keepout on layer 3 because there's no actual
> HDMI signals.  there's some setting... somewhere... which makes a
> difference on GND copper pour / plane on layers 1, 3 and 6, where GND
> plane on 2 and 5 use a different clearance.  i found it... *once*...
> about 2 years ago.
> 
> if it really really matters i can look around but it'll be a pain to find.

After spending a couple minutes studying layers 3 and 4, here's what I see:
1.  It looks like there may be a difference in the signal via antipads on layers 3 and 4 and that would be a way for us to give just that handful of vias special properties--if need be--although in this case it interestingly looks like the antipads are larger on layer 4 than layer 3.  (optical illusion?)
2.  The (minimum?) polygon size or line width of the fill looks larger on layer 3 than layer 4.

I think the second point, or something along those lines, likely explains the void on layer 3 and lack of void on layer 4.  It looks like if we were to find and adjust that fill parameter on layer 3, some of your explicit guard traces might become redundant. (I can see why you added them because the ground fill wasn't working as expected.)

It would be nice to change layer 3 to make the signal path more uniform on the way through the vias but it's not the end of the world if we can't, as long as layers 2 and 5 resemble layer 4 in the vicinity of the HDMI differential signal vias adjacent to the A20.  

>> I know, the curve is beautiful, but I think we can still improve the
>> situation with straight lines.  They had more space and thus changed
>> the trace width to effect the change in impedance.  We on the other
>> hand have an unwanted change in impedance due to unavoidable
>> constriction of clearance.  Since the obstacles are immovable and
>> cause an abrupt change in impedance, we have the option of tapering
>> the clearance in order to soften the abruptness--and thus the
>> reflection coefficient.
>> 
>> In other words, what you have done coincides with my idea of the best
>> course of action.
> 
> oh! :)

The remaining questions are where do we impose 5mil clearance (by bringing in the fill), where do we start tapering, and what does the taper look like?  Likewise, but in reverse order, at the other end.

>>>>>> Is the closest copper on layer 1, around the A20, 5mil from the HDMI
>>>>>> differential signals?
>>>>> 
>>>>> yes.  everything's 5 mil design rule.
>> 
>> I agree that 5mil is the design rule.  The question is, "How close did
>> we actually get?"  What I'm referring to as foreign copper is any
>> trace, via, component land/pad, or fill that is not part of the
>> differential pair under consideration.  In other words, did we make it
>> from A20 land to via without getting closer than 10mil?  7mil?  We can
>> adjust the proximity of ground fill with a manual keepout if we need
>> more space so I'm not too worried about that.  I'm more curious about
>> distance to other traces, lands/pads, or vias.
> 
> ok - let me re-run the flood fill and do a quick review, starting from the A20.
> 
> so.  layer 1.  surrounded, all 5mil.  tracks are only 60mil or so to
> the VIAs.  didn't do a keepout.  all 5mil.
> 
> layer 3 (the VIAs) - some sort of curve on the flood-fill, it's 5mil
> but there's a void in the middle.

Are layers 2, 4, and 5 also 5mil away from the differential signal at the vias?

> layer 6, starts @ 5mil, expands out to 15mil (mostly).  exceptions:
> distance to TX2 "long wiggle" is 7mil,  distance from bottom VIAs
> along board edge (to TXC), 11.2mil, distance to track *between* the
> VIAs 15mil.  distance to GND vias ABOVE the hdmi tracks (TX2), 19mil.
> 
> in theory then i could move the entire set of horizontal tracks up
> by... 4 mil... i reeaallly don't want to though as it means redoing
> the whole f*****g lot of wiggles.... argh :)

Can't select and move?  That does stink!  Evening out the clearance does help lower the difference in impedance seen by the traces in the TXC pair (one had 15mil to foreign signal, the other 11.2mil) and the TX2 pair (one had 15mil to foreign signal, the other 19mil).  Impedance imbalance between the traces of a differential pair moves energy from differential mode to single-ended mode (between trace and reference) which will try harder to radiate (EMI).

Since it is such a long section it would be beneficial to move the traces.  If we were to redraw the wiggles I would suggest we take care to separate parallel sections of the same trace by at least 4 times the trace width (4*5mil=20mil)--especially for TX2.[Toradex, p. 17]  This is because at these frequencies, if the same trace is too close and parallel, the signal will hop straight across.

So if we bring in the keepout at 5mil on layer 6 and taper it slowly to 7mil by the point we get to the TX2 wiggle which exhibits 7mil clearance.  To make this work we have to start the pairs off around 5mil inter-pair spacing and then spread them as we taper the keepout.  I realize this is more complicated than what I first described.

> at the other end all bets are off for distances after we get to the ESD pads.
> 
>>>>>> What is the distance to the closest copper to the HDMI signals at the ESD lands?
>>>>> 
>>>>> 5 mil
>> 
>> Is that from the distance between ESD lands/pads or proximity of other
>> traces or vias?
> 
> there are no other traces other than GND.  there are no other VIAs
> other than GND.   the pad-to-pad clearance is about... 7mil.  actually
> because of the keepout the flood-fill stays away... sooOo... some of
> the VIAs are 5mil, the rest are maybe... 7mil.
> 
> 
>>>>>> What is the distance to the closest copper to the HDMI signals at the
>>>>>> connector lands?
>>>>> 
>>>>> 5 mil
>> 
>> Again, is that from the distance between connector lands/pads or
>> proximity of other traces or vias?
> 
> ok it's the taper i put into the keepout.  there are no other traces,
> there is only GND vias.   the taper in the keepout is the only point
> where the GND flood-fill gets to within 5mil.
> 
> i'll redo some pictures.
> 
>> [...]
>>> ah.  ok.  it's components.  so, the EMI components, and the VIAs.
>>> and if the hand-drawn keepout isn't quite the right distance.    ah.
>>> and IPSOUT (main power DC line) which i've just adjusted to be outside
>>> the 15mil boundary.
>>> 
>>> and... from the A20's pins: i put a GND trace round the back of the
>>> VIAs because the next row up includes all the USB signals.  i didn't
>>> feel comfortable leaving that without a separation (again, 5mil
>>> clearance).
>> 
>> Both sound fine.  We just want to establish at what point we can
>> consider 15mil clearance a reasonable expectation and see whether we
>> can make the transition smoother (less abrupt).  And then, by the same
>> token, at what point we are constrained to a smaller clearance so that
>> we can again smooth the transition.
> 
> yehhh there are so many GND vias at the ESD end i'd question its
> effectiveness...

You'd question the effectiveness of what?  The ESD component?  The taper?

>  the VIAs can't be moved, it's the only way  they can
> get in on the DC3 connector.
> 
>>>>>> What is the minimum frequency we will be running the HDMI at?  (With
>>>>>> version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
>>>>>> on each data line.  Thus I would expect good edges if we design for
>>>>>> harmonics of 34GHz.;>)
>>>>> 
>>>>> :)  1920x1080p60.  honestly though if it works at 1280x720p60 i'll be happy.
>>>> 
>>>> Again I wasn't clear enough with the question--I misled you by
>>>> mentioning the highest clock frequency.  To calculate the length
>>>> characteristic for this taper, I need to figure out the lowest
>>>> frequency (minimum) for which we want it to exhibit this impedance.
>>> 
>>> ah: i missed "minimum" rather than "maximum".  ok 640x480 at 30hz is the
>>> lowest possible resolution that people would use...
>> 
>> Is 1920x1080p60 is the maximum supported resolution under HDMI v1.4?
> 
> yehyeh.
> 
>> If so then 340MHz clock likely coincides with 1920x1080p60.
>> =>340MHz * 640/1920 * 480/1080 * 30/60 =
>> 340MHz * 1/3 * 4/9 * 1/2 ~= 25MHz
> 
> yehyeh.
> 
>> Well, that implies data rate of 250MHz and harmonics of 2.5GHz, and
>> wavelength = velocity of propagation / frequency
>>  = 150um/ps / 2.5GHz = 6mm ~= 236mil
>> 
>> So if we can determine the closest encroachments then we can try to
>> adjust the keepouts to ease between clearances.
> 
> cool.