[Arm-netbook] HDMI High-Frequency Layout: Recommendations

[Richard Wilbur]

On Wed, Sep 20, 2017 at 4:22 PM, Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Wed, Sep 20, 2017 at 8:27 PM, Richard Wilbur
> <richard.wilbur at gmail.com> wrote:
>
>>>>  I'm interested to see what
>>>> holes/voids and connections the power and ground planes have.
>>>
>>>  there are *no* connections on the GND planes.  the power plane (and
>>> GND layers) interestingly have done a full surround on the HDMI vias.
>>> remember i had to separate them by an unusual distance.
>>
>> What clearance to the fill do you have on the HDMI differential signal
>> vias on layer 3, as opposed to 2, 4, and 5?  I see it leaves a void on
>> layer 3 but not on layer 4 (or presumably 2 or 5).
>
>  yehyeh.  to be honest: i don't know exactly.  or, i worked it out a
> long while ago, and can't remember precisely what it was.

Isn't it in the keepout of the HDMI differential signal vias on layer 3?

>> I'm not looking to provide any special connection to the power or
>> ground pins.  I just want to make sure we don't obstruct the return
>> current path any more than necessary on its way from bottom reference
>> ground plane (layer 5) to top reference ground plane (layer 2) to the
>> power supply pins of the differential drivers:
>> 1.  ground plane (layer 2) via to SoC ground pin land (layer 1)
>> 2.  ground plane (layer 2) via to power supply decoupling capacitor
>> ground land (layer 1), through decoupling capacitor to land on power
>> supply trace (layer 1), through trace to SoC power supply pin land
>> (layer 1).
>>
>> The goal is to avoid unnecessarily impeding this return current path.
>> I'm trying to avoid making the path >~200mil and putting any major
>> obstruction (like a huge layer void) in the way.
>
>  ok - i think i understand.  the distance from the first set of vias
> to the nearest decoupling capacitors is 180mil.  those are all at the
> centre of the A20 processor.

Sounds decent.

>>>> I've read a little (not nearly as much as I'd like, but I lack time)
>>>> about using a taper to match impedance differences while minimizing
>>>> the reflection coefficient.[*]  I'm thinking we can use it at both
>>>> ends of this layout to great advantage.  We taper from 5mil clearance
>>>> around the A20 on layer 1 to 15mil clearance on layer 6.  Later we
>>>> taper from 15mil clearance to whatever the closest copper is at the
>>>> ESD and connector lands.
>>>
>>>  that's something that it would be helpful to have a rough diagram,
>>> even if it's hand-drawn [but see below: i think i understand it]
>>
>> Once I figure out the frequency => characteristic taper length
>> situation I'll try to send a drawing and/or image.  In the meantime
>> I've been looking at [*].
>
>  ooo wow fascinating.
>
>  hmmm... a bit too much to implement though.  PADS can't really
> conveniently handle that kind of drawing (ok it can but it's a
> complete fricking pain.  you're limited to 45 degree angles, and the
> mouse-drag is.. erratic in what it decides to allow you to move ).

I know, the curve is beautiful, but I think we can still improve the
situation with straight lines.  They had more space and thus changed
the trace width to effect the change in impedance.  We on the other
hand have an unwanted change in impedance due to unavoidable
constriction of clearance.  Since the obstacles are immovable and
cause an abrupt change in impedance, we have the option of tapering
the clearance in order to soften the abruptness--and thus the
reflection coefficient.

In other words, what you have done coincides with my idea of the best
course of action.

>>>> Is the closest copper on layer 1, around the A20, 5mil from the HDMI
>>>> differential signals?
>>>
>>>  yes.  everything's 5 mil design rule.

I agree that 5mil is the design rule.  The question is, "How close did
we actually get?"  What I'm referring to as foreign copper is any
trace, via, component land/pad, or fill that is not part of the
differential pair under consideration.  In other words, did we make it
from A20 land to via without getting closer than 10mil?  7mil?  We can
adjust the proximity of ground fill with a manual keepout if we need
more space so I'm not too worried about that.  I'm more curious about
distance to other traces, lands/pads, or vias.

>>>> What is the distance to the closest copper to the HDMI signals at the ESD lands?
>>>
>>>  5 mil

Is that from the distance between ESD lands/pads or proximity of other
traces or vias?

>>>> What is the distance to the closest copper to the HDMI signals at the
>>>> connector lands?
>>>
>>>  5 mil

Again, is that from the distance between connector lands/pads or
proximity of other traces or vias?

[...]
>  ah.  ok.  it's components.  so, the EMI components, and the VIAs.
> and if the hand-drawn keepout isn't quite the right distance.    ah.
> and IPSOUT (main power DC line) which i've just adjusted to be outside
> the 15mil boundary.
>
>  and... from the A20's pins: i put a GND trace round the back of the
> VIAs because the next row up includes all the USB signals.  i didn't
> feel comfortable leaving that without a separation (again, 5mil
> clearance).

Both sound fine.  We just want to establish at what point we can
consider 15mil clearance a reasonable expectation and see whether we
can make the transition smoother (less abrupt).  And then, by the same
token, at what point we are constrained to a smaller clearance so that
we can again smooth the transition.

>>>> What is the minimum frequency we will be running the HDMI at?  (With
>>>> version 1.4 the highest clock is 340MHz which implies 3.4GHz data rate
>>>> on each data line.  Thus I would expect good edges if we design for
>>>> harmonics of 34GHz.;>)
>>>
>>>  :)  1920x1080p60.  honestly though if it works at 1280x720p60 i'll be happy.
>>
>> Again I wasn't clear enough with the question--I misled you by
>> mentioning the highest clock frequency.  To calculate the length
>> characteristic for this taper, I need to figure out the lowest
>> frequency (minimum) for which we want it to exhibit this impedance.
>
>  ah: i missed "minimum" rather than "maximum".  ok 640x480 at 30hz is the
> lowest possible resolution that people would use...

Is 1920x1080p60 is the maximum supported resolution under HDMI v1.4?

If so then 340MHz clock likely coincides with 1920x1080p60.
=>340MHz * 640/1920 * 480/1080 * 30/60 =
340MHz * 1/3 * 4/9 * 1/2 ~= 25MHz

Well, that implies data rate of 250MHz and harmonics of 2.5GHz, and
wavelength = velocity of propagation / frequency
  = 150um/ps / 2.5GHz = 6mm ~= 236mil

So if we can determine the closest encroachments then we can try to
adjust the keepouts to ease between clearances.