[Arm-netbook] rk3288 ddr ram initialisation reverse-engineering.... a ray of hope!

[Luke Kenneth Casson Leighton]

yay i believe i may have _finally_ tracked down the issue with the
DDR3 RAM initialisation - not the actual underlying problem with the
PCB layout (which is down to impedance and is probably going to need
insertion of a bank of... probably like... 60-80 resistors...
*sigh*...) but with initialising the RK3288 RAM controller at the much
lower clock rate of 200mhz.

i _really_ should have checked the rkclk_configure_ddr function in
u-boot-rockchip's clk_rk3288.c file first, but i have to say it's been
great fun doing reverse-engineering again.  i basically took the
rkbin/rk32/ 32_LPDDR2_200MHz_LPDDR3_200MHz_DDR3_200MHz_20150318.bin
file which rockchip supplied - and which is confirmed as successfully
initialising the DDR3 controller (at 200mhz) on the EOMA68-RK3288
board - and have been rapidly working it back towards c-code.

... probably unnecessarily as it turns out, because *actually* what i
quite likely only needed was to add "200mhz" as one of the supported
switch-statements in rkclk_configure_ddr!  ooops....

now, it has to be said that if i had not got as far through the
reverse-engineering as i have, i would not have had the information
that i needed in order to easily work out the PLL settings for the
200mhz clock-rate.

the reason is quite straightforward: the proprietary binary is
SIGNIFICANTLY more comprehensive in its initialisation,
parameterisation, safety-checking and follow-up testing of the memory.
i can see _where_ the u-boot-rockchip sdram initialisation comes from:
many of the functions are the same but the key strategic ones are
significantly improved.

so, anyway, it's late evening, so i cannot go round to my host's house
straight away and test this out, but i will do tomorrow first thing :)

l.

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