[Arm-netbook] eoma68 rk3288 testing

[Luke Kenneth Casson Leighton]

On Tue, Mar 7, 2017 at 7:22 PM, Hrvoje Lasic <lasich at gmail.com> wrote:

> I am not sure if we understand each other here. Impedance of your lines are
> not function of thickness of board and thickness of line but thickness of
> prepreg and thickens of line.

 understood (and not expressed clearly before that i understand).  so
please adjust prior reading to understand that i was talking about the
distance between each of the 8 layers being reduced to 6mil (on a
1.2mm stack) where they were, in the Reference Design, well over 10mil
(on a 1.6mm stack).

 PADS has an unusual feature in that you can specify the stack
entirely, including distance between layers, thickness of copper
between layers, dielectric constant of each prepreg and also the
dielectric constant and thickness of coatings top and bottom.

 from that - and the thickness of tracks - PADS can calculate an
advisory figure for impedance for each pin-pair or net.  it can't do
invdividual traces unfortunately.

 i've been using this feature to do investigations, it matches well
with the capability of the javascript-based calculator you kindly
posted.


> So, for thickness of your lines you need to match with thickens of prepreg
> to be able to meet certain impedance. it does not mean that your total PCB
> thickens must be changed, you can vary some other layers of preprag, there
> are number of options with producers of PCB.

 the amount by which the prepreg of the required layers (1, 3 and
8)would have to be changed  is so great as to *require* the total PCB
thickness to also be changed.  that cannot happen because then the
case would not fit: there is a hard limit of 4.8mm.  1.2mm is for the
PCB, 1.9mm for TOP components, and 1.6mm for BOTTOM.  it's therefore
simply *not possible* to go beyond a 1.2mm PCB thickness.  the
micro-sd card would need to be removed, for a start, a new type of
PCMCIA connector sourced (due to the altered height).... i don't
believe the processor would even fit.

 also, increasing the thickness of the lines to beyond 4mil is also
not possible, because this is a 0.6mm pitch BGA and there simply isn't
room to get the lines out from between 2 BGAs (it's already only
clearance of 3.5mil).

 there *really is* no way to even *begin* to look at doing anything
*remotely* like a redesign, as the design constraints are so strict
and so complete that what i have is *literally* the only option.

 yes i tried with 6 layer only but the routing of micro-sd, LCD, eMMC
and GPIO was so horrendous that it was just far too risky to
contemplate (as in: almost certain to fail).  as it was, it was six
weeks before i was happy to even put $1.5k towards the (resultant)
8-layer board.

 anyway.  i'll be back at my host's house later today, so can test out
ZQ auto-calibration, see what happens.  must rest.

l.