[Arm-netbook] HDMI High-Frequency Layout: Recommendations--Taper

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Dec 27 21:10:02 GMT 2017

On Wed, Dec 27, 2017 at 8:51 PM, Richard Wilbur
<richard.wilbur at gmail.com> wrote:
>> when i show X-ray-mode gerbers layers 1 & 2 i mark in yellow at top a
>> proposed modification, look good?  you can see to pin 4 there is that
>> GND via, the shape of the hole gets really weird / sharp edges there.
> I'm not seeing the weird / sharp edges so you must have fixed them?

 i think so... you checked the video?  i''ll do a close-up tomorrow
(5am here now)

>> also i'm aware that the layer 2 and 5 bottom-most
>> curved-shaped-keepout-holes are about 1 mil too far to the left, see
>> yellow (SE corner) where i'll move them both over.
> Again, I'm not seeing a problem so you must have fixed it.
>>> 2.  At the west boundary I see your point regarding layers 4 and 5.
>>> Looks like you have made a good solution.
>>> I suppose you could add 5mil additional overlap.
>>> How much overlap does it currently have?
>> currently arouuund 9mil roughly.
>>> How much opening from the edge of the keepout
>>> on layer 4 to the edge of the closest connector pads?
>> around 4mil.  tracks are 5mil so can use that as a scale.
> In that case I think you have done enough.  The overlap looks good.

 whewwww :)

>>> Some of the adjustments on layer 6 might be taken care of by
>>> modifying the net groups to create an "HDMI High-Frequency"
>>> group which contains only the differential pairs {HTX2P, HTX2N, HTX1P,
>>> HTX1N, HTX0P, HTX0N, HTXCP, HTXCN}, apply the 15mil conditional
>>> clearance rule to that group.
>> that's what's already done :)
>> oh, except to VIAs i kept it at 5mil, now i remember.   15 mil to
>> landing pads, 15 mil to tracks, 5mil to VIAs i think this was because
>> i didn't want the holes made by VIAs to be too large.  what you think?
>> make them 15mil too?
> I'm not as worried about the holes left by the vias on the east (connector) end as the west (processor) end of the differential pairs if we expanded clearance to 15mil.  I'm guessing we have more current flowing through layers 2,4,5 over there.  I guess the question boils down to, "Where are the power sources and sinks (including decoupling capacitors) relative to the HDMI high-frequency signal vias?"  If the vias make holes on a line connecting power sources to sinks, then we need to either make sure there is plenty of copper providing a path around the holes or minimize the size of the holes.

 i'll check it again tomorrow but the 5VDC runs along layer 4 right
underneath the HDMI long E-W traces.  layer 4 3V3 plane was a dog's
dinner mess that i had to tidy up last year, and, actually, removing
the legacy TSSOP-48 NAND finally actually allowed me to adjust things
so that it wasn't a total swiss cheese.

 in geeeneral i'm happy with the power / GND layout, i've been paying
attention to it.


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