[Arm-netbook] Libre RISC-V RV64GC SoC

[Andrew M.A. Cater]

On Wed, Dec 27, 2017 at 09:08:42AM +0000, Luke Kenneth Casson Leighton wrote:
> so, ahh i would say it's christmas come early but it really *is* christmas :)
> 
> i've been speaking with madhu, the head of the shakti team, they're
> extremely busy with a tapeout deadline of 1st january 2018, so in
> about a month or so's time he will have more time to talk, and it will
> be possible to begin properly planning.
> 
> unlike many people to whom i've pitched the idea of an entirely libre
> SoC, madhu instead responded, "ok sure, what would you like?".
> initially being rather confused by this positive response, i outlined
> this page http://rhombus-tech.net/riscv/shakti/m_class/ and slowly
> began asking more questions.
> 
> it turns out that the indian government has given him a mandate to
> create THE entire range of computing platforms.  in speaking to him
> about why, well it was pretty obvious: if you were to have everyone in
> india buy a foreign imported smartphone - and that's just one market -
> it would LITERALLY bankrupt the country with the exodus of cash.  so
> they have a law requiring that foreign countries, if they wish to sell
> product in india, that 70% of it must be manufactured locally.  apple
> has apparently asked if they can work around this to get more
> foreign-made smartphones into india... they've been told unequivocably
> NO.
> 
> the sheer scale of the opportunity has not only companies - you can
> guess who they are - trying to bribe him to shut down the entire
> programme, but also companies offering free tools and more.  this
> means that with a ZERO financial outlay it is possible to get three
> (only three) designs through tapeout *AND* the MVP (multi-vendor
> programme) which will result in around 100 sample bare dies being made
> (entirely free), of which maybe 30% of those can be expected to
> actually result in a functioning chip.  that's still 30 chips for a
> zero financial outlay where normally the cost would be around $5m, one
> each at at 20nm, 28nm and one more at 40nm.
> 
> the only condition is: the entire SoC *must* be entirely libre.
> that's right down to the bedrock: not just the entire ASIC design but
> also the software stack running on it.  you know the reasons why:
> "Intel Management Engine".
> 
> it just so happens that the overlap between what we would like to see
> happen and what the shakti team has been set up to achieve happen to
> align near-100%.
> 
> this is an incredible opportunity.
> 
> there are four main tasks / details which need to be taken care of:
> 
> * designing and specifying the SoC so that it is DESIRABLE in a
> specific target market or markets
> * finding the right team(s) of people with links to the free software
> community to target 3D, Video and so on.
> * finding a customer base large enough to warrant going to production
> * bridging finance (if that customer base isn't going to pay cash up-front).
> 
> now, it turns out that *IF* the processor is designed SUCH THAT it is
> desirable for use in the indian schools market - either as laptops,
> netbooks, tablets or desktop machines (laptops would be better), THEN
> it is a near-automatic process of getting to market, orders of 10
> million units are not a problem.
> 
> note that *this is exactly what the EOMA68 Libre Laptop Housing is
> for*, and would be an immediate base on which to get demo units in
> front of people, very very quickly (just have to take care of making
> an EOMA68-RISCV64 Card).
> 
> so, any ideas, input etc. welcomed.
> 

Talk to Debian for the software, obvs :) They have most things packaged
somwehere and ties to Debian Edu/Skolelinux. The problem, if problem it 
is, is that you need a new port to do this well and that means good
emulators and, eventually, fast build hardware. 

RISCv64 also needs to be well supported by the Linux kernel, so you
probably need to make sure that there's an easy way to build the Linux
kernel (GCC build chain and GNU tools ... )

Andy C.

> l.
> 
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