[Arm-netbook] HDMI High-Frequency Layout: Impedance

[Richard Wilbur]

On Thu, Aug 3, 2017 at 9:28 AM, Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Thu, Aug 3, 2017 at 2:59 PM, Richard Wilbur <richard.wilbur at gmail.com> wrote:
>> What I said earlier is that I would recommend the following geometry
>> for the transmission lines:
>> trace width = 6.5mil
>
>  there's not enough space.  when i said "there's not enough space" i
> *really meant*, "there's not enough space".  it *might* be possible to
> increase to 5.1 mil but i think you'd agree it would not be worth it.
>
Below find the revised treatment of the latter part of the discussion
in light of the facts you enumerated.

"""
Turns out there isn't enough room to route 6.5mil traces.

W<mil> S<mil> Z(single-ended) Z(differential)
              <Ohm>           <Ohm>
5      5      72.1            111
5.1    5      71.5            111
5.2    5      71.0            110
*Table* of single-ended and differential impedances for geometries
constrained by lack of board space.

These impedances fall in the +/-15% margin of the nominal 100 Ohm
differential impedance [85,115]Ohm.

Reviewing with reference to TI's "Routing Guidelines"[20]:
i.  Use the smallest trace spacing possible, which usually is
specified by your PCB vendor:  in our case 5 mils
ii.  Make sure the geometries obey:
    a.  S < H;  (S = 5mil) < (H = 6.4mil)
    b.  S < W; (S = 5mil) < (W = 5.1mil)
    c.  W < 2H; (W = 5.1mil) < (2H = 12.8mil)
    d.  D > 2S = 10mil
Looks like we abide by their guidelines if we use the 64.6 Ohm
single-ended impedance values.  Likewise, we can still meet all the
margins if we use 5.1mil trace width and 5mil spacing.  It seems the
distance, D, to the next trace is somewhat flexible because in this
reference it is reduced from 3S to 2S.  (I'm sure 3S is better than
2S, if you have the space.)

Ground Planes under Pads

Toradex mentions the lower impedance between wide traces and the
reference plane causing impedance mismatch at large pads for
components and connectors.[21]  The width of the pads in the
illustration are 5-6x the width of the traces connecting to them.  On
the micro-HDMI connector the width of the pads is around 0.2mm (JAE
DC3R019JA7R1500 pad width = 0.23 +/-0.03 mm ~= 9.1 +/- 1.2 mil), and
the pads are lined up on 0.4mm centers.  This implies that the spacing
is 0.4mm - (0.23 +/-0.03mm) = 0.17 -/+0.03mm ~= 6.7 +/-1.2mil
W<mil> S<mil> Z(single-ended) Z(differential)
              <Ohm>           <Ohm>
 7.9   5.5    58.9             93.0  [DC3 lands, w-tol, s-tol]
 7.9   7.9    58.9            100    [DC3 lands, w-tol, s+tol]
 9.1   6.7    54.5             89.9  [DC3 lands, nominal]
10.3   5.5    50.7             80.0  [DC3 lands, w+tol, s-tol]
10.3   7.9    50.7             86.5  [DC3 lands, w+tol, s+tol]
*Table* of single-ended and differential impedances for geometries
constrained by micro HDMI connector lands.

These differential impedances are all within JAE's 100 Ohm +/-25% =
[75,125] Ohm.  The best thing to do here would most likely be to ease
the transition from the main trace impedance to the connector
impedance over a distance.  Where they are close to a via, we could
ease up to the via width from the normal trace width over a few mil.

Via Impedance

If and when we start supporting HDMI v2.0+ we will need to tune the
impedance of our signal vias even more keenly as our signals will
surpass the 10GHz barrier.[22]  Presently we also have the happy
situation that since our high-frequency signal vias always connect
between top and bottom layers, our stub length is 0 on signal vias.
Creating transparent (tuned) vias requires familiarity with a 3-D EM
simulator and some time to set up, run, evaluate results of
simulations, and then repeat in order to tune the impedance.  (See
section below "Libre Field Solvers".)

We can still take some of the recommendations to heart:
1.  Use minimal size vias for high-frequency traces to reduce
parasitic capacitance.[23]
2.  Place the two vias of the differential pair in close proximity to
increase capacitive coupling between the signals.(smaller via pitch)
3.  Instead of using two separate anti-pads on signal vias, combine
them into an oval shared antipad (on every layer) to reduce parasitic
capacitance.
4.  Place ground vias next to signal vias to provide low-impedance
ground-return paths.[22, Figure 2]
"""