[Arm-netbook] HDMI High-Frequency Layout: Impedance

Richard Wilbur richard.wilbur at gmail.com
Thu Aug 3 14:59:15 BST 2017

On Thu, Aug 3, 2017 at 7:11 AM, Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Thu, Aug 3, 2017 at 12:37 PM, Richard Wilbur
> <richard.wilbur at gmail.com> wrote:
>> Here we can see the effect of changing the single-ended impedance on
>> width and spacing of traces in a differential pair of given
>> differential impedance.  By raising the single-ended impedance we
>> reduced both the width of the traces and also the spacing.
>  i know from DDR3 that they can change (dynamically) the end-impedance
> both on the SoC and in the DDR3 RAM ICs.  it means you can stick with
> a particular track width and spacing then have the SoC and DDR3 ICs
> adjust each end to suit.

Interesting trick with the SoC and DDR3 RAM ICs.  What I was talking
about is how we can change the single-ended impedance of our design
while holding the differential impedance at 100 Ohm and what effect
that has on trace width and spacing.  If we reduce the trace width and
spacing but maintain 100 Ohm differential impedance, our single-ended
impedance goes up!  It's not exactly rocket science.  When we narrow
the traces we have less capacitive coupling to ground so you might
expect our single-ended impedance would rise.

>> Toradex mentions the lower impedance between wide traces and the
>> reference plane causing impedance mismatch at large pads for
>> components and connectors.[21]
>  yehyeh.  fortunately the ones on the DC3 connector are tiny.
>  i think you're saying we're ok here with 5mil track, 5mil spacing,
> and lots and lots of ground vias.  i can't get them in between the
> diff-pairs though.

Close.  What I am saying is that the DC3 connector pads and spacing
actually look pretty close to row 2 of the table (55 Ohm single-ended
impedance) for 100 Ohm differential trace geometries.  So I don't
think the DC3 lands will cause a large impedance discontinuity.  In
other words no need to obstruct the ground reference plane from under
the DC3 lands.

What I said earlier is that I would recommend the following geometry
for the transmission lines:
trace width = 6.5mil
trace spacing = 5mil
offset from other copper in the same layer >= 10mil (ground shield
trace, other differential pair, etc.)

We'll primarily need ground vias where the signal changes layers and
thus the return current needs to change from one ground reference
layer to the other.  If we do a pretty decent job of squashing the
skew and the differential drivers on the chip give us a signal with
little common-mode energy to start with, we won't need much of any
shielding between pairs.  Since the ground shield will be asymmetric
(only on one side of a pair) I would recommend keeping it as far away
as possible so it will have less asymmetric effect on the impedance.

I have two more sections in mind:  Libre Field Solvers and
Recommendations (Specific to this Layout).
The first is more than half researched and written.  I think it can be
finished in another couple hours.
The second is a little more fluid as I plan to make some
recommendations/suggestions and ask some questions which will allow me
to refine those recommendations or suggestions.

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