[Arm-netbook] crowdfunding page is live -- and different CPUs for the future

[Manuel A. Fernandez Montecelo]

2016-07-18 01:38 Luke Kenneth Casson Leighton:
>
>> MIPS it's a more realistic possibility, but I am not sure if IC1T is a
>> very good option, if it has no foothold in the market yet, has zero
>> distributions supporting it, and it doesn't offer clear advantages in
>> other areas (??).  I wouldn't mind at all to get one of those, but I am
>> not sure if many people will follow... so would be bad in terms of
>> effectiveness.
>
> if it can't have debian... yeah.  as in, because the open64.net
>compiler "isn't called gcc", it's almost impossible to *do* a debian
>port.

As you probably know, but others perhaps not, it's not just a matter of
the compiler, but also to port many many software packages and
submitting patches upstream and take care of this for years.

For ARM, MIPS, SPARC, PowerPC and the rest of non-Intel-but-well-known
it's maybe not 100% perfect, but there are Debian (or other distros/OSs)
ports working almost as well as the best ones.  But I suppose that for
IC1T it's not the case at all, so it would need a lot of effort also in
the software front, for years.


>> If it's for something more experimental like perhaps the IC1T would be,
>> I'd consider the possibility of exploring RISC-V [1] based designs like
>> the recently launched SiFive ones [2].
>>
>> The development is more in-line with FOSS (even if some aspects are not
>> 100% perfect), hopefully there will be no need for blobs or NDAs or
>> problems for booting.  And with 64-bits, it is well prepared to be
>> usable for several decades to come [3].
>
> ok, what goes into a successful SoC?  let's go through ths list:
>[...]
>
>... but if you *don't do* that licensing, and instead try to replicate
>them all, you are immediately placing the entire project at risk.
>bear in mind that TSMC won't talk to you if you make a failed chip
>(first time) because you're wasting their time.  and it costs $USD 2
>*MILLION* for the production masks (the lithographic masks like an OHP
>plastic sheet)

I don't really have any idea about the fabrication processes, but
according to this:

  https://dev.sifive.com/documentation/freedom-u500-platform-guide/

  "The resulting customized U500 SoC is optimized for manufacture in a
  TSMC 28nm metal-gate process, and delivered as packaged tested parts
  by SiFive."

and contains most of the technologies that you mention, except video,
but maybe the custom accelerators can substitute traditional GPUs.

I am not sure if all of this is freely licensed, or how it works.

With lowrisc cores, if they become available in the next few months,
they should be freely licensed.


>... so against that background can you see that to focus on the
>*actual* processor's *instruction set* - to make a totally new
>architecture - is pretty much irrelevant as far as making an *actual
>processor* is concerned?
>
> and then once that's done you *still* need to port OSes to it!

Yeah, I agree.  I was only saying that if one's going to go out of
her/his way and consider IC1T for a future option, RISC-V can be a more
interesting and future-proof alternative *than IC1T* (not better than
ARM or MIPS at the moment).

Also, that I'd consider to do this only a few years down the line, not
now -- and focusing only in the A20 at the moment.


>my feeling is, we would be much better off talking to Loongson and
>seeing if they'd be up for a licensing deal of their MIPS64
>architecture.  apart from anything the Loongson 3G and above have
>emulation in hardware of the top 200 x86 instructions which makes it
>possible for them to accelerate non-native QEMU up to 70% of the
>native MIPS64 processor's clock rate.  which is pretty awesome.

Yeah, Loongson would be also good, although I am not sure if they will
keep it active or if they'll abandon it in favour of others.


Cheers.
-- 
Manuel A. Fernandez Montecelo <manuel.montezelo at gmail.com>