[Arm-netbook] Allwinner outsells Intel

[joem]

On Fri, 2013-05-10 at 14:08 +0300, Paul Sokolovsky wrote:
> Hello,
> 
> On Fri, 10 May 2013 12:39:48 +0200
> Vladimir Pantelic <vladoman at gmail.com> wrote:
> 
> []
> > You assume you can transfers one 32bit word over GPIO for every CPU 
> > instruction, but as you wrote you need some kind of control logic
> > around that, so at best you will need 10-20 instruction per 32 bit
> > word. So now you are using 20-40% of your CPU for this data transfer
> > and as you want to chain CPUs, you need that done twice.
> > 
> > Also, on existing SoCs most GPIO HW blocks are not even able to reach 
> > that high data rates at all.
> 
> That's said very mild. GPIO and other external interfaces are 
> "always*" run on a clock different from CPU core, and that clock is
> "always*" (much) lower than CPU clock. 100MHz is damn good GPIO
> toggle speed, aim for less in many cases.
> 
> Here's a random prooflink:
> http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/49018.aspx
> 
> 
> * Prove otherwise with a datasheet for a 200MHz+ CPU.

Need only 21MHz toggle speed GPIO pins required for 800x600 24 bit 60
fps video transferred over 32 bit bus. If use 64 bit, it halves to
11MHz. Easily doable.

Anyway wait and see - this is going too far ahead - we still don't have
a working board yet to begin these experiments, and as said earlier,
priority is elsewhere.