[Arm-netbook] github.com/slapin/a13board , was: expeyes-SBC, minimalist A10 board

Paul Sokolovsky pmiscml at gmail.com
Sat Jun 8 16:35:24 BST 2013


Hello Sergey,

On Sat, 4 May 2013 04:12:24 +0400
Sergey Lapin <slapinid at gmail.com> wrote:

[]

> Hi, people! As you seem to have a clue, could you please review
> DDR3 on github.com/slapin/a13board ?

As I didn't see any replies, maybe you could elaborate where you
yourself see issues in your design. For example, knowing that Kicad
doesn't have any helpers/checks for track length matching, I thought
that writing a standalone tool to do post-check would be useful, but
turned out that it's exactly what you have with your nets.py! (Well,
might be worth to add constraint file, so you can just run it and it
tells you DRC pass/fail).

I see that important tracks are not perfectly matched, e.g.:

91: /DRAM/DDR3_DQS0 len = 7.288377
92: /DRAM/DDR3_DQS0_N len = 7.955295
93: /DRAM/DDR3_DQS1 len = 9.912792
94: /DRAM/DDR3_DQS1_N len = 10.372883

But I'm not sure what tolerance should be there.

Other questions I would have:

1. It seems that your board was attentively designed with low-cost
production in mind, being 5x10cm. What about replacing NAND with
microSD, ditching some stuff - do you think it would be possible to fit
it in 5x5cm given Kicad constraints (which is all manual routing as far
as I understand)?

2. What about 2-layer board? I know, I know, they say that you at least
should have GND layer between top and bottom signal layer. But well,
there's no GND layer between signals on the same layer (though they
recommend routing GND track between signals, yeah!). And generally,
that "you need at least 4 layers" comes from the same industrial
pundits who then put DIMM sockets on motherboards (whoa, those
mechanical contacts must have crazy impedance and capacitance, and yet
it works), and who's going to stop marking SMD resistors to "save
environment", in other words, that can be yet another industrial B/S.

3. Generally, I wonder if A13 can be made to work with classy DDR after
all. The idea is not to chase for "highest throughput" design
(Allwinner is not such anyway), but to have really personal-fab board
for router and similar usages. And real slowness is always in software.


> 
> Thanks a lot,
> S.
> 

-- 
Best regards,
 Paul                          mailto:pmiscml at gmail.com



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