[Arm-netbook] Pictures of tracks under A10 chip

[jm]

On Tue, 2012-11-27 at 12:14 -0800, cpinc at rogers.com wrote:
> >Robert - yes please. Nice to have pictures of tracks on both sides.
>  
> Hi Joe,
> 
> I sent the image to your email address.
>  
> As mentioned, the DDR RAM is the biggest challenge, then the impedance
> matching which I tweak based on PCB material.
> PCB  manufacturers can also make the final impedance adjustments or
> provide you the proper values to use.
>  
> Robert

Robert, that image is fantastic!
It would greatly speed up design work.

A couple of questions:

1. The inner BGA pads and some of the other bga pads have thick tracks.
   Will those tracks have issues with solder freezing?
   Is it better off to have min track width to the pads to prevent that?
2. What is the bga pad size?
3. What is the min track width used in the design between the bga pads?
4. What is the hole size for vias used in the design between bga rows of
pads?
5. What is the overall via size used in the design for vias between the
bga rows of pads?

>From some other conversation I remember
the tracks the engineers used were 5 mils with 5 mil clearance.
The vias are 16 mils.
The drills were around 5 or 6 mils.

The companies I know makes PCB with these limits
min track width 0.075mm
min hole size 0.15mm.