[Arm-netbook] Fwd: Exynos4412 Quad Core Board

[lkcl luke]

On Sun, Jul 15, 2012 at 12:32 AM, Dr. David Alan Gilbert
<dave at treblig.org> wrote:
> * lkcl luke (luke.leighton at gmail.com) wrote:
>> On Sat, Jul 14, 2012 at 11:47 PM, lkcl luke <luke.leighton at gmail.com> wrote:
>>
>> >> Still, it would be great to find prices on the module and details
>> >> of the EBI.
>> >
>> >  does anyone know where the exynos 44xx datasheet can be obtained from?
>>
>>  http://en.wikipedia.org/wiki/External_Bus_Interface
>>
>>  ok, well apparently it's a standard, typically used to access NAND or
>> SDRAM, but happily general-purpose enough to access any
>> memory-addressable device (DM9000)
>>
>>  right.  also, amazingly, there does actually exist an SATA-I PHY IC
>> from ATMEL: Atmel:AT78c5091 - datasheet's here:
>> http://www.dzjsw.com/jcdl/a/AT78C5091.pdf
>>
>>  the main job is done: conversion to/from 8-bit parallel is handled.
>> it looks like quite a lot of discrete components would be needed in
>> order to give it an actual memory address, which could then be
>> read/written using DMA from the EBI bus, but that's not too hard.
>
> Going through 8-bit parallel is hardlyworth the bother;

 it's what comes out of those ICs, but the data rate will be a hell of
a lot faster than USB.  that's 8-bit parallel at up to 500mhz so
that's 500mbytes/sec (the speed that RAM operates at) whereas USB can
only max out at 480/8 = 60mbytes/sec.

 however that SATA-I PHY can only do 1500mbits/sec, 10-bit encoded for
each 8-bit byte, so that's 150 mbytes/sec.  soo, even the
300mbytes/sec of SATA-II, if you could find an SATA-II PHY, would
still be within the limit of that 500mhz 8-bit bus.

 assuming that there's a DMA controller on the exynos 44xx that will
handle memory transfers in 8-bit reads of the same location into a
sequential (stepped) location (and likewise for writes).  you *really*
don't want to be tying up CPU in a tight loop doing reads and writes
at 150mbytes/sec!

but if it was absolutely absolutely necessary i'm sure it would be
possible to put a data latch IC down, converting 2 8-bit reads/writes
into 1 16-bit read/write which would at least mean you'd only be doing
tight-loop reads/writes at 75mhz not 150.

 bottom line: even that AT78c5091 and worst-case doing byte-banging is
better than what USB2 can do.  he said.  tentatively.

 /peace.

 l.