[Arm-netbook] EOMA-CF

[lkcl luke]

On Sun, Jan 22, 2012 at 9:16 PM, Bari Ari <bari at onelabs.com> wrote:
> On 01/18/2012 12:01 PM, lkcl luke wrote:
>> my mum is a camera enthusiast.  got a nice digital SLR.  the funny
>> thing is, it takes CompactFlash cards.  which i hadn't actually
>> handled for quite some time.
>>
>> so, it came as something of a shock for me to pick one up, and see
>> just how tiny it is.  i know it's technically possible to fit CPU, RAM
>> and NAND into that small a space, but when you actually look at it,
>> it's like... wow.  are we _really_ going to have a fully-functioning
>> stand-alone computer with micro-hdmi, USB-OTG, headphones socket and a
>> MicroSD slot?
>>
>>
> If the A10 was available in POP package then a CF card would be viable.
> As it currently is the DDR bus would probably have to slowed to be able
> to fit external DDR into the board space of CF

 ah nooo, they don't.

> since all the traces have to be of equal length.

 an application note from fujitsu on DDR3 shows in section 4.2 General
wiring restrictions that you do "wiggly-snakes" on the
balanced-diffierential lines (such as clock).  it describes very
specifically what you must and must not do to achieve this (in order
not to throw off significant RF at the corners of each wiggle) and
figure 1-1 on page 5 illustrates it very clearly, and shows that the
DDR3 RAM ICs are only 1cm away from the CPU.

 wits-tech's PCB layout does exactly the same thing.  if you look
closely at some of the wiggly-snake lines, you can see that some of
them, one line goes directly to a pin, whilst the other one hooks
round it and goes in 180 degrees directly opposite!

 also, the fujitsu app note explains for example in section 4.7.4 that
you can have between 31 and 44.7mm for what they call the MCNTL and
MCMD groups (A0-14, BA0-BA2, CAS, RAX, WE, CKE, CS and ODT)

however because we have 4 MCNTL+MCMD groups, one per DDR3 RAM IC, i
believe it is possible to use the absolute minimum 31mm because there
*is* no 2nd RAM IC per group to daisy-chain to.

then there is a second appnote i found by a guy called barry olney of
in-circuit design pty which outlines all of the critical design
requirements for ddr3, on page 4.

from these and a little bit more reading around, i concluded that the
wits-tech stuff looked actually like it was following the guidelines
correctly, including making sure that the number of VIAs was kept to a
minimum, and that any differential lines which had to use VIA
through-holes did so in the advised manner.

now, from all that, and from both the diagram that fujitsu did and
also the wits-tech layout i concluded that it was perfectly reasonable
to fit 2-4 DDR3 RAM ICs into a CF card space, and in fact comparing
what i naively cut/paste from the EVB picture to create the EOMA-CF
example with what wits-tech came up with, they're pretty much
identical:

http://hands.com/~lkcl/ddr3-a10.png
http://elinux.org/images/thumb/e/ed/A10_compact_flash.png/600px-A10_compact_flash.png

l.

p.s. in the cut/paste example i created, i didn't do 4 DDR3 RAM ICs,
but you can see it's perfectly possible... you couldn't also have 2x
NAND ICs as well, that would be insane.