[Arm-netbook] DDR3...

[lkcl luke]

rrright.  i think i get this DDR3 RAM thing (connection-wise).
http://rhombus-tech.net/allwinner_a10/ddr3_ram_09jan12.png

biiig picture :)

things wot i kinda worked out (mostly from the TI document):

* There are 4 ICs, divided into Banks 0,1 and each IC in each Bank
i've labelled A and B.  so there is A0, B0 and A1, B1.

* Chip-Select 0/1, Clock-Enable 0/1 and ODT 0/1 are there to select
"banks", like if you have 2 slots of SO-DIMMs.

* x16 means you can connect data bits 0-15 from the CPU's DDR3
controller to ICs designated "A", and data bits 16-31 to ICs
designated "B".

* in an x86 environment, the DDR3 controller would have 64 bit data
addressing: tough luck, we ain't got that: there's only 32-bits [hint,
hint to gordan about why you can't do SO-DIMMs :) a DDR3 "funnel"
controller would be needed.... yuk]

and i've just realised i made an error on the MDQ lines *sigh*....

help!

l.