[Arm-netbook] CT-PC89E: set_lcd_power decode

[Luke Kenneth Casson Leighton]

would anyone like to help decode this into its relevant GPIO function(s)?

* BIC 0xNN is equivalent to x &= ~0xNN
* ORR 0xNN is equivalent to x |= 0xNN
* LDR R3, R1, #0xA8] is equivalent to R3 = (uint32*)((int)(R1+0xA8))

and 0xA8, when you look at the header files, shows it to get
S3C_GPIO.. er.... BANKF + 0x8 which makes that ... err... BANKF is
2-pin-jobbies so... iit's pullup! yes, pullup, he says.  and
0x30000000 is 0x3>>(14*2) so that bit from C01DAEBC to C01DAECC is
definitely a BANK F pullup on pin 14, setting it to 0x2 (0x2>>(14*2))

i've already put the constants S3C_VA_GPIO = 0xF4600000 and
S3C_VA_TIMER = 0xF4300000 into the mix.

the code you need to look at is really the 2.6.24.2 kernel,
"arch/arm/plat-s3c24xx/gpio.c" and use ctags to get at the relevant
constants.

l.

RAM:C01DAE94 set_lcd_power                           ; CODE XREF:
midfun_keypdown_timeout+34p
RAM:C01DAE94
RAM:C01DAE94 oldR11          = -0xC
RAM:C01DAE94 oldSP           = -8
RAM:C01DAE94 oldLR           = -4
RAM:C01DAE94
RAM:C01DAE94                 MOV     R12, SP
RAM:C01DAE98                 STMFD   SP!, {R11,R12,LR,PC}
RAM:C01DAE9C                 SUB     R11, R12, #4
RAM:C01DAEA0                 CMP     R0, #0
RAM:C01DAEA4                 LDR     R1, =S3C_VA_GPIO
RAM:C01DAEA8                 LDR     LR, =S3C_VA_TIMER
RAM:C01DAEAC                 BEQ     loc_C01DAF08
RAM:C01DAEB0                 LDR     R3, [R1,#0xA0]
RAM:C01DAEB4                 BIC     R3, R3, #0x30000000
RAM:C01DAEB8                 ORR     R3, R3, #0x20000000
RAM:C01DAEBC                 STR     R3, [R1,#0xA0]
RAM:C01DAEC0                 LDR     R3, [R1,#0xA8]
RAM:C01DAEC4                 BIC     R3, R3, #0x30000000
RAM:C01DAEC8                 ORR     R3, R3, #0x20000000
RAM:C01DAECC                 STR     R3, [R1,#0xA8]
RAM:C01DAED0                 LDR     R3, [R1,#0xA0]
RAM:C01DAED4                 BIC     R3, R3, #unk_C0000000
RAM:C01DAED8                 ORR     R3, R3, #0x40000000
RAM:C01DAEDC                 STR     R3, [R1,#0xA0]
RAM:C01DAEE0                 LDR     R3, [R1,#0xA8]
RAM:C01DAEE4                 BIC     R3, R3, #unk_C0000000
RAM:C01DAEE8                 STR     R3, [R1,#0xA8]
RAM:C01DAEEC                 LDR     R3, [R1,#0xA4]
RAM:C01DAEF0                 ORR     R3, R3, #0x8000
RAM:C01DAEF4                 STR     R3, [R1,#0xA4]
RAM:C01DAEF8                 LDR     R3, [LR,#8]
RAM:C01DAEFC                 ORR     R3, R3, #1
RAM:C01DAF00                 STR     R3, [LR,#8]
RAM:C01DAF04                 LDMFD   SP, {R11,SP,PC}
RAM:C01DAF08 ; ---------------------------------------------------------------------------
RAM:C01DAF08
RAM:C01DAF08 loc_C01DAF08                            ; CODE XREF:
set_lcd_power+18j
RAM:C01DAF08                 LDR     R3, [R1,#0xA0]
RAM:C01DAF0C                 BIC     R3, R3, #0x30000000
RAM:C01DAF10                 STR     R3, [R1,#0xA0]
RAM:C01DAF14                 LDR     R3, [R1,#0xA8]
RAM:C01DAF18                 BIC     R3, R3, #0x30000000
RAM:C01DAF1C                 ORR     R3, R3, #0x10000000
RAM:C01DAF20                 STR     R3, [R1,#0xA8]
RAM:C01DAF24                 LDR     R3, [R1,#0xA0]
RAM:C01DAF28                 BIC     R3, R3, #unk_C0000000
RAM:C01DAF2C                 ORR     R3, R3, #0x40000000
RAM:C01DAF30                 STR     R3, [R1,#0xA0]
RAM:C01DAF34                 LDR     R3, [R1,#0xA8]
RAM:C01DAF38                 BIC     R3, R3, #unk_C0000000
RAM:C01DAF3C                 ORR     R3, R3, #0x40000000
RAM:C01DAF40                 STR     R3, [R1,#0xA8]
RAM:C01DAF44                 LDR     R3, [R1,#0xA4]
RAM:C01DAF48                 BIC     R3, R3, #0x8000
RAM:C01DAF4C                 STR     R3, [R1,#0xA4]
RAM:C01DAF50                 LDR     R3, [LR,#8]
RAM:C01DAF54                 BIC     R3, R3, #1
RAM:C01DAF58                 STR     R3, [LR,#8]
RAM:C01DAF5C                 LDMFD   SP, {R11,SP,PC}
RAM:C01DAF5C ; End of function set_lcd_power