[Arm-netbook] libre 64-bit risc-v SoC
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 4 15:33:32 BST 2017
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, May 4, 2017 at 3:29 PM, mike.valk at gmail.com <mike.valk at gmail.com> wrote:
> 2017-05-04 12:51 GMT+02:00 Luke Kenneth Casson Leighton <lkcl at lkcl.net>:
>> ha, bit of irony for you: gaisler research released the LEON3 SPARCv8
>> core a number of years ago under the GPLv2, so that people could use
>> it for "academic and research purposes", the expectation being that
>> for "commercial" use, they would seek a license from gaisler because
>> you can't mix GPLv2 source with proprietary hard macro source.
>> the irony / beauty is: by seeking out *specifically* hard macros even
>> for DDR3 that are compatible with the GPL, no proprietary license is
>> needed :)
>> so... the source code which implements SMP cache coherency for a
>> multi-core LEON3... i can pull that out and use it :)
> Uhhm. So your going to use the GLP'ed macro for "SMP cache coherency" from
> the LEON3 SPARCv8 design into the RISC-V so you can build a Multi core (SMP)
> Or are you considering a new SoC SPARC design?
no. not enough mind-share
> According to wikipedia there is also a LEON4. If it is based on the LEON3
> then the source code should be available right?
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