[Arm-netbook] Arm Netbook, Saw the update,

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jul 17 08:16:46 BST 2017


---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Mon, Jul 17, 2017 at 7:26 AM, Richard Wilbur
<richard.wilbur at gmail.com> wrote:
>>> On Jul 4, 2017, at 09:50, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>>>
>>> On Tue, Jul 4, 2017 at 4:15 PM, Richard Wilbur <richard.wilbur at gmail.com> wrote:
>> […]
>>> A couple questions that spring immediately to mind:
>>> 1.  How continuous are the ground planes under the differential pairs?  (Are there voids in the ground planes under the differential pairs?)
>>
>> no.  layers 2 and 5 are solid ground planes.  vias obviously go
>> through those , full vias only.  non-GND vias also obviously create
>> small interruptions but that's all
>
> Wonderful!  That's music to my ears.  No major obstacles on return current path except the vias.  So when we change signal layers, we'll need adjacent ground plane-to-ground plane vias to provide a nice low-impedance path for the return current in the ground planes.

 i've added as many of these as i can fit.  space is... very very tight.

>>> 2.  The intra-pair length sounds well-matched, my understanding of the inter-pair skew is that the requirement is in terms of the clock speed Δt <= 0.2 Tcharacter.  For 225 MHz clock the application note spoke of 888ps.  So we'll be interested in determining the maximum clock rate and speed of propagation.
>>
>> 3e8 m/sec * 888e-12 = 0.2664 metres.... which is 266.4 mm... way
>> beyond anything which would indicate some kind of problem if the board
>> is 78mm long and the skew is only 2mm.
>
> You're on the right track and that is a good calculation for propagation in free space (vacuum).  It turns out with relative permittivity of FR-4 fiberglass substrate our signal actually travels significantly slower which tightens our design parameters a little.

 oh!  duh!  i forgot about that

> Not too awful.  Just a few questions about how you are routing to control the impedance.
> 1.  Are you using a 2-D field solver to determine the impedance and adjust design parameters accordingly(trace width, intra-pair spacing, inter-pair spacing, etc.)?

  PADS can calculate impedance based on board stack, track width and
track-to-track spacing... i'm... relying on that, and the fact that
the tracks are 50mm long.

> 2.  Are you working with your board fabricator to determine the design parameters mentioned above b

 nnaahh.



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