[Arm-netbook] HDMI High-Frequency Layout: Recommendations

Richard Wilbur richard.wilbur at gmail.com
Thu Aug 17 17:20:34 BST 2017

On Aug 16, 2017, at 22:22, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On Thu, Aug 17, 2017 at 12:01 AM, Richard Wilbur
> <richard.wilbur at gmail.com> wrote:
>> […]
>> I would also look carefully at the GND traces separating the differential pairs from board edge and other circuitry.  If we can't put 15mil between the differential pair traces and these GND traces, I would remove these GND traces as well.  If we have to remove the GND traces between differential pairs and other circuitry, this will at least have the happy effect of providing 15mil spacing between the differential pair and that other circuitry.
> flood-fill will just end up putting them back - i'd have to set a
> copper-to-trace separation @ 15mil as well.

Sounds like just the ticket.  So you have a flood-fill on the bottom layer?  Is the flood-fill connected to GND?  Can you set the 15mil copper-to-trace separation as a property of the differential traces?

The goal with this 15mil clearance is to space other copper in the same plane far enough away to have a negligible effect on the differential impedance of the differential pair and by the same token negligible high-frequency signal coupling.  The microstrip differential pair geometry is based on having ground plane (may it extend forever ;>) underneath the traces separated by a dielectric of thickness t.  (We took that into account in the impedance calculations.  Actually power and ground are identical from the perspective of high-frequency signals so we could have built our microstrip differential pair over a power plane--or even moved from one reference plane to another.  If we change reference planes, then we need to provide a low-impedance at high frequency path for any return current.  Since we used two different ground planes, plated through-hole vias work well.  If we had used planes at different potentials we would couple through capacitors.)

> there's one place where the diffpairs go past the main power line
> (IPSOUT) - that's got a 5 mil copper GND separating it at present: i'd
> be nervous about taking that out.

I wouldn't worry because that 5mil copper GND has 5mil spacing on each side, thus ensuring 15mil between the closest differential trace and power.  That should be sufficient.

On the other hand, if I remember correctly the proximity to IPSOUT happened because we decided to do significant inter-pair skew compensation close to the power circuit.  If we remove that inter-pair compensation, we may have enough space to keep that ground trace around IPSOUT and still make our 15mil clearance around the differential pairs.

The other thing that we can do if we have a little extra space after taking out the intermediary GND shield traces and inter-pair skew compensation wiggles is distribute the intra-pair skew compensation closer to the sources of intra-pair skew--corners.  Right now you've done a great job of compensating for intra-pair skew in the first segment:  from CPU lands to first via.  Then there are some very significant wiggles when we first get to the bottom layer and I don't see any other intra-pair skew compensation all the way out to the connector.

If we can do it, the most effective place for intra-pair skew compensation is within 15mil of the skew source--right before or after a bend.  If skew originates in a bend and is resolved by a complementary bend within 15mils, then we don't need to add anything specific.

If we distribute the intra-pair skew compensation as outlined above we will likely be able to accomplish it with some pretty small wiggles which may fit more easily into the available space.

>> 1.  The receiver has the capability to recover up to 5 bit times of inter-pair skew,
> o arse: *receiver* not transmitter.

No problem then.  But it sure highlights the importance of having the correct perspective when thinking about the problem.:)  (I have trouble with it too, at times.  The right perspective often makes the problem much more tractable.)

>> Toradex suggests we limit the inter-pair skew in the traces to 1/4 of that value or 0.5 * T(bit) which corresponds to a length of 22mm.
> 22 mm... okaaay.
>> From what I've seen, even without inter-pair skew compensation in the layout the inter-pair skew you observed was ~8mm < 22mm.
> 9.  or so.   okaaay now i get it.

You can see how I came to the conclusion that we will likely be fine without any inter-pair skew compensation--with even a pretty generous engineering margin.

>>>> Are you talking about moving the differential pairs further
>>>> from the edge of the board?
>>> yes. but from what you're saying it's not possible anyway.
>> How far are the differential traces from board edge at present?
> 0.9mm -> 35 mil.
> to the nearest vias is 0.2mm -> 0.787mil

How far is the board-edge ground shield trace from the edge of the board?  From the closest differential pair trace?  How wide is the board-edge ground shield trace?

I'm guessing you meant the closest vias to the differential pair traces are 0.2mm = 7.87mil?  Are these the ground-to-ground vias for low-impedance connection of reference planes?  (Low-impedance return path close to signal vias?)

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