[Arm-netbook] libre 64-bit risc-v SoC

[Hendrik Boom]

On Fri, Apr 28, 2017 at 10:51:49PM -0500, ryan wrote:
> 
> 
> On 04/28/2017 05:56 PM, Bill Kontos wrote:
> >
> >Out of curiosity has anyone ever attempted to prototype a 
hardware block
> >based on evolution principles? Doing it on an fpga is probably a bad idea
> >since we wont be able to implement the results in more copies but this
> >could potentially also happen in a software simulation where the input
> >and output interfaces of the hardware block are pre defined
> >
> ><snip>
> 
> I suspect that without having the feature of it being an instruction set
> that only works on that one chip due to it exploiting the quirks of the
> chip, some efficiency would be lost.
> 
> I'm imagining a system where traditional silicone grooms many FPGAs, each
> with a dedicated task, and the system is provided with some known-good
> instruction sets that work, but only slowly. So then either the OEM or the
> user sets up their fancy new system, and one of the steps is to plug it in
> and run a setup program for anywhere from a few hours to a couple of days
> which iterates the instructions to improve efficiency, then they can begin
> to use their system.
> 
> As for using this method in a software simulation, I wouldn't be surprised
> if some chip manufacturers already do that for certain sections of the
> chip, even if its only during the early design faze. I would imagine the
> software guiding the evolution could be instructed to cull anything that
> isn't working with binary, thus allowing human engineers/programmers to
> more easily reverse engineer the instruction set and further edit it.

Let me remind you of a real-world situation.  The hardware designers 
were woring on the second version of their successful CPU.  They 
attached some counters to masure hos many times the varioun 
instructons were being executed.  THey discovered that the most 
common instructons were certain test and brnch instructions.  So they 
worked hard on making sure the next model had the most efficient 
implementation of those test and branch instructions they could 
achieve.

But when they finally put the new machine together and tried it out, 
they foud no improvement at all.

Investigating, they discovered they had optimized the wait loop.

-- hendrik