[Arm-netbook] LowRISC : a CPU open-sourced down to the silicon level, based on RISC-V architecture

Manuel A. Fernandez Montecelo manuel.montezelo at gmail.com
Fri Aug 8 18:58:50 BST 2014

2014-08-07 20:02 Luke Kenneth Casson Leighton:
>On Thu, Aug 7, 2014 at 6:58 PM, Manuel A. Fernandez Montecelo
><manuel.montezelo at gmail.com> wrote:
>> 2014-08-07 16:33 Guillaume FORTAINE:
>>> http://www.lowrisc.org
>> Is this any different in concept from OpenRISC 1000 (or1k)?
>> http://opencores.org/or1k/Main_Page
> by a long margin: yes.  OpenRISC i don't believe was ever planned to
>run at the kinds of speeds that RISC-V plans to operate at.
>http://riscv.org/download.html#tab_rocket shows that they are
>producing benchmarks for operation at 1ghz.  the RISC-V architecture
>appears to be designed as 64-bit from the ground up, and there also
>appear to be room for instruction set extensions as well:

I do not know if there's an issue with speed limits of or1k, and it's
true the part about 64 bits.

There's more info here, and and interesting discussion in comments,
look for example the comments from Jeremy Bennett comparing both:


In short, other than the possibility that physical chips available for
purchase might be more likely from lowrisc, there do not seem to be
many technical differences.

>> With or1k we have already ~6.6k architecture-dependent (that have to
>> be compiled) source packages from Debian available, and being updated
>> whenever they are uploaded to Debian unstable.  These are readily
>> available for simulations and for people who can synthesise this in a
>> FPGA.
> http://riscv.org/getting-started.html
> full toolchain, port of qemu, and an FPGA port.
> no debian port yet though. biiit early for that :)

OpenRISC or1k has all of this as well, that's the reason why the
Debian port was able to start.

I don't know how the quality and completeness of toolchain/qemu/etc
implementations compare, though.


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