[Arm-netbook] ARM SOC Pricing

[Bari Ari]

On 01/18/2012 12:03 PM, Henrik Nordström wrote:
> It's 4+1. You run either the single low-power core or up to quad high-power cores, they can not run at he same time. It can switch between the two modes pretty fast however. The different cores are even made at different manufacturing processes to optimize powera/performance in the two modes.
>
> So little work, single lowpower core, increasing load and switch over to the high poer cores, as many you need up to 4.
>
> I can imagine that the details in how it switches may be interesting as for a short while you have no cores running...
>
> ----- Ursprungsmeddelande -----
>> Tegra3 is actually 5-core according to the info I can find, but the 5th
>> core is asymmetric.
>
http://www.linuxfordevices.com/c/a/News/ARM-CortexA7-and-bigLittle/

Cortex-A7 chip will team up with -A15 in 'big.Little' combo SoCs

The idea behind the architecture is to have both a Cortex-A7 and a 
Cortex-A15 reside on the same SoC, as suggested by the ARM illustration 
at right. The lower-power Cortex-A7 would be used for basic tasks like 
social media, audio playback, telephony, and running an operating system.

The Cortex-A15 would be used for the more compute intense workloads, 
such as navigation and gaming. Power management software would select 
the right processor for the right jobs in a fashion that would be 
transparent to the user, enabling up to a 70 percent extension in 
battery life, claims ARM.

ARM officials said switching from one chip to another in the big.Little 
design will take 20 microseconds, assisted by ARM's AMBA 4 ACE Coherency 
Extensions. AMBA 4 ACE is said to enable the switching of workloads 
between two processors, while ensuring full cache, I/O, and chip-to-chip 
coherency between the processors and across the system.