[Arm-netbook] [review] SoC proposal

lkcl luke luke.leighton at gmail.com
Thu Feb 9 01:46:46 GMT 2012

On Wed, Feb 8, 2012 at 10:57 PM, Alec Ari <neotheuser at ymail.com> wrote:
> I had a feeling I was missing something from the picture. My apologies.

 naah s'all'right, alec.  i understand it's kinda "wtf??" :)  take a
look at the xtensa architecture on the tensilica web site.  it's
deeply impressive.  leaving aside that tensilica already have video
decode covered (albeit in ultra-low-power), their architecture is so
flexible that it would i believe be an absolute cinch to "dial up" a
SIMD floating point unit per processor (times 8).  the real kicker is
not to go _too_ overboard!

 if you've got direct first-hand experience of the types of low-level
operations involved in 3D i could... damn, i could really have used
your help last year: i put out a call on the various mailing lists for
some help in evaluating what was needed at the assembly level for 3D
primitives and got no response.

 it would be really good to be able to get an idea of exactly what are
the inner loops, what's the most intensive operations, where's the
processing power actually needed, to get optimal results.  are MIPS
"on the ball" or is there a better way?


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