Hello Luke and others!
Are there any news about the cards? We're slowly reaching the next estimated shipping date (30 September), so let us know if there's anything new (I know the answer for the shipping date is the same as always).
I also have a stupid question: would it be possible to combine the power of several computer cards, so that all GPUs together would be capable of running real time 3D graphics?
Also good job with Libre SoC, I look forward to see it ready and working! Thank you for your commitment to libre hardware. Proprietary hardware is really annoying and often unusable, especially on free operating systems, making their adoption harder. Your work is crucial.
Jan Wielkiewicz
On Fri, Sep 18, 2020 at 12:41 AM Jan Wielkiewicz tona_kosmicznego_smiecia@interia.pl wrote:
Hello Luke and others!
hi jan
Are there any news about the cards? We're slowly reaching the next estimated shipping date (30 September), so let us know if there's anything new (I know the answer for the shipping date is the same as always).
i'm pinging mike to find out where he's at. will let you know.
I also have a stupid question: would it be possible to combine the power of several computer cards, so that all GPUs together would be capable of running real time 3D graphics?
as a beowulf style cluster? of course :)
Also good job with Libre SoC, I look forward to see it ready and working! Thank you for your commitment to libre hardware. Proprietary hardware is really annoying and often unusable, especially on free operating systems, making their adoption harder. Your work is crucial.
appreciated, jan. i got up and running on an FPGA a couple weeks ago (Versa ECP5) https://www.youtube.com/watch?v=72QmWro9BSE
l.
Luke Kenneth Casson Leighton wrote:
i'm pinging mike to find out where he's at. will let you know.
I appreciate the update Luke, thanks.
As a friendly reminder: please let us know what we can do to help both with technical issues, time on some work that differently technical people can help with, or money.
If there's already a document listing this which I need to read, please give me the URL and I'll read that.
Thanks again.
On Sat, Sep 19, 2020 at 1:39 AM J.B. Nicholson jbn@forestfield.org wrote:
Luke Kenneth Casson Leighton wrote:
i'm pinging mike to find out where he's at. will let you know.
I appreciate the update Luke, thanks.
As a friendly reminder: please let us know what we can do to help both with technical issues, time on some work that differently technical people can help with, or money.
thanks JB.
If there's already a document listing this which I need to read, please give me the URL and I'll read that.
the main thing right now i think is developing and thinking through the DTB overlay fragments, continuing the conversation that paul started. also one thing that's essential is that library function which needs to be submitted upstream to the linux kernel and u-boot to get the I2C EEPROM ID at address 0x51 and use that to decide which overlay to read.
so the data format for the I2C data also needs to be defined. that could be as simple as the USB (and PCIe) IDs.
l.
On Sep 18, 2020, at 07:09, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: […]
i got up and running on an FPGA a couple weeks ago (Versa ECP5) https://www.youtube.com/watch?v=72QmWro9BSE
Congratulations on the success of booting the libre SoC on FPGA. Which processor instruction set architecture are you folks using?
Looks like the toolchain for that FPGA has a free/libré license?[*] Did I misread the Lattice Semiconductor announcement?
If it’s really free/libré I might have to save my pennies for one of those boards!
Sincerely, Richard
Reference: [*] http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5VersaDev...
On Tue, Sep 22, 2020 at 5:13 PM Richard Wilbur richard.wilbur@gmail.com wrote:
On Sep 18, 2020, at 07:09, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote: […]
i got up and running on an FPGA a couple weeks ago (Versa ECP5) https://www.youtube.com/watch?v=72QmWro9BSE
Congratulations on the success of booting the libre SoC on FPGA. Which processor instruction set architecture are you folks using?
OpenPOWER ISA.
Looks like the toolchain for that FPGA has a free/libré license?[*]
yes. nextpnr5, developed by daveshah and others. yosys talks to that, through something called trellis.
Did I misread the Lattice Semiconductor announcement?
no - the *lattice* toolchain is proprietary.
If it’s really free/libré I might have to save my pennies for one of those boards!
nextpnr5 is a bitch to compile because it uses python-boost by default. all you need do there is compile "--disable-boost --disable-python" or something like that, you'll have to investigate, and you get a non-GUI toolchain (you don't need or want the GUI anyway).
i recommend getting both the ulx3s https://www.crowdsupply.com/radiona/ulx3s
*and* also the VERSA-ECP5 https://nl.mouser.com/ProductDetail/Lattice/LFE5UM-45F-VERSA-EVN
the reason is because the VERSA-ECP5 has a 1 gigabit DDR3 IC on it, plus some other stuff that the ULX3S doesn't have, *but* the ULX3S has an SDRAM IC which is a lot simpler, is SDR, and so we can sort-of test against that and then have reasonable confidence that the ASIC will work. ULX3S also has an SDcard slot on it.
l.
Dnia 2020-09-18, o godz. 14:08:29 Luke Kenneth Casson Leighton lkcl@lkcl.net napisał(a):
On Fri, Sep 18, 2020 at 12:41 AM Jan Wielkiewicz tona_kosmicznego_smiecia@interia.pl wrote:
Hello Luke and others!
hi jan
Are there any news about the cards? We're slowly reaching the next estimated shipping date (30 September), so let us know if there's anything new (I know the answer for the shipping date is the same as always).
i'm pinging mike to find out where he's at. will let you know.
Sooooo did you find out anything? By the way, I just saw you're doing a code freeze of the processor. Do you have any estimations of when the first products using the simple version of the core may be available? I have some pocket money hungry for crowdfunding.
Jan Wielkiewicz
On Wed, Nov 4, 2020 at 7:58 PM Jan Wielkiewicz tona_kosmicznego_smiecia@interia.pl wrote:
Dnia 2020-09-18, o godz. 14:08:29 Luke Kenneth Casson Leighton lkcl@lkcl.net napisał(a):
On Fri, Sep 18, 2020 at 12:41 AM Jan Wielkiewicz tona_kosmicznego_smiecia@interia.pl wrote:
Hello Luke and others!
hi jan
Are there any news about the cards? We're slowly reaching the next estimated shipping date (30 September), so let us know if there's anything new (I know the answer for the shipping date is the same as always).
i'm pinging mike to find out where he's at. will let you know.
Sooooo did you find out anything?
he had to move to a bigger factory, and will be carrying on the production.
By the way, I just saw you're doing a code freeze of the processor. Do you have any estimations of when the first products using the simple version of the core may be available?
mmm...
I have some pocket money hungry for crowdfunding.
right now they'll need to be big pockets, it's costing NLnet EUR 18,000 to do a few test ASICs (maybe 30, of which maybe 15 might work).
we also need to be very careful in whom we give them to because we are required to comply with the OPF's EULA. if it's non-compliant with the OpenPOWER Compliance Requirements, we can't sell it. however... there is a leeetle wiggle-room inasmuch as IBM and other entities would have to show "material harm" caused by our test ASIC.
if we sold 100,000 such non-compliant test ASICs such that people start doing upstream kernel development to cater for the mistakes, that starts to piss people off who make literally billions of dollars from the reputation going back 25 years of OpenPOWER ISA being "unified, stable and reliable".
if however we sold... mmm... 1000 on the SPECIFIC condition that UNDER NO CIRCUMSTANCES was this to be considered anything other than a test ASIC, then *MAYBE* it would be ok.
l.
arm-netbook@lists.phcomp.co.uk
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J.B. Nicholson -
Jan Wielkiewicz -
Luke Kenneth Casson Leighton -
Richard Wilbur