HDMI Layout Notes for EOMA68 Cards by Richard Wilbur
Impedance
Trace Impedance: 100 Ohm +/-15% differential[11][12], 55 Ohm +/-15% single-ended[3] (90 Ohm +/-15% differential, 50 Ohm +/-15% single-ended[3])
There seems to be some small disagreement between sources on the differential trace impedance for HDMI high-speed signals. Chrontel[11], Texas Instruments[12], and JAE[13] all quote 100 Ohm but with different tolerances--Chrontel +/-10%, Texas Instruments +/-15%, JAE +/-25% (in connector area[13])--while Toradex[3] quotes the goal as 90 Ohm +/-15%. These ranges overlap but the normal variation in manufacturing is more likely to exceed the limits of the acceptable range if we design to the wrong goal!
90 Ohm +/-15% = [76.5, 103.5] Ohm 100 Ohm +/-15% = [85, 115] Ohm
It seems the consensus is on 100 Ohm +/-15% for the differential impedance.
Toradex mentions something else which helps with the selection of design parameters: "The differential impedance is always smaller than twice the single-ended impedance"
Z(differential) < 2 * Z(single-ended)[14] => Z(single-ended) > Z(differential) / 2
Thus, if we wish to have Z(differential) = 100 Ohm +/-15%, we should choose the single-ended impedance such that
Z(single-ended) > (100 Ohm +/-15%) / 2 = 50 Ohm +/-7.5%
Toradex suggests 55 Ohm single-ended impedance to coincide with 100 Ohm differential impedance.[15]
In order to model and calculate expected impedance we need to describe the geometry of the arrangement of traces, reference planes, and dielectric layers in the PCB.
PCB Dimensions (not drawn to scale or even to correct aspect ratio): ______ ^ T (thickness of copper in signal layer) v _______________________________ ^ H (thickness or height of insulator) v _______________________________ reference plane (GND or Power) _______________________________
The 6-layer FR-4 PCB chosen for EOMA68-A20 has the following characteristic dimensions: total thickness of PCB = 1.2mm ~= 47.3mil H(height of dielectric between outer copper layer and adjacent reference plane) = 6.4mil copper cladding = 1oz min{W(trace width)} = 5mil min{S(trace-to-trace space)} = 5mil min{diameter(plated through-hole vias)} = 6mil diameter(via surround/pad) = 12mil
To calculate the thickness (T) of 1 ounce copper requires several conversion factors and the density of copper. "1 ounce copper" refers to the thickness of 1 ounce (avoirdupois versus troy) of copper spread over 1 square foot. There is at least one web site which purports to calculate the thickness in mils of a particular weight of copper cladding[16], but they use some pretty heavy approximations for otherwise well-known conversion factors and conclude that 1.37 mil = 1 oz Cu. I used the standard unit conversion factors as shown below:
Given: Areal density = 1 oz Cu / ft^2
Exact conversion factors: 1 (avoirdupois) oz = 28.349523125g [17] 1 ft^2 = (1ft * 12in/1ft * 2.54cm/1in)^2 = (30.48cm)^2
Empirical value: Density (Cu pure) rho = 8.96 g / cm^3 [18][19: CRC, LNG]
Calculation: T = areal density(given) * conversion(oz->g) / (volume density) / conversion(ft->cm)^2[16] T = 1 oz Cu / ft^2 * 28.349523125g / 1 oz * 1 cm^3 Cu / 8.96 g Cu * 1 ft^2 / (30.48cm)^2 = 0.003405711cm Cu = 0.03405711mm * 1in / 25.4mm * 1000mil / 1in = 1.34mil Cu (Using 8.92 gCu / cm^3 [19: WEL] => T = 1.35mil Cu)
The most well-attested value for copper's density was 8.96 g/cm^3 yielding T = 1.34mil Cu. Illustrating the sensitivity of the calculation to variation of parameters, the minority density value of 8.92 g/cm^3 yielded T = 1.35mil Cu.
Microstrip PCB Dimensions (not drawn to scale or even to correct aspect ratio):
<-W-><--- S ---><-W-><----- D -----> __IIIII___________IIIII___________________IIIII Signal:+ - x W = design width of trace S = spacing between traces of differential pair (+,-) D = spacing to unrelated signal "x" (another pair, ground shield, etc.)
Texas Instruments gives some equations to help calculate trace geometries for 100 Ohm differential impedance.[12]
Z(differential) = 2 * Z(single-ended) * (1 - 0.48 * exp(-0.96 * S / H)) Z(single-ended) = 88.75/sqrt(relative permittivity + 1.47) * ln(5.97 * H / (0.8 * W + T))
Since the board material and manufacturing process specify the parameters: relative permittivity(FR-4) = 4.4[1] H = 6.4mil T = 1.34mil and the HDMI standard specifies: Z(differential) = 100 Ohm we have two equations in three unknowns: Z(single-ended), W, S
Given the guidance that Z(single-ended) > 50 Ohm, we can solve the second equation for W(Z(single-ended)),
W<mils> = 7.463 * H * exp(-Z(single-ended) * sqrt(relative permittivity + 1.47) / 88.75) -1.25 * T
Then select a value for Z(single-ended), turn the crank and see what value of W we come up with. After looking at the result we may decide to select a different value for Z(single-ended) and calculate the concomitant W in order to find a routable trace width and a usable single-ended impedance.
Let's try this for Z(single-ended) = 55 Ohm. W(Z(single-ended) = 55 Ohm) = 7.463 * 6.4mil * exp (-55 Ohm * sqrt(4.4 + 1.47)/88.75) - 1.25 * 1.34mil = 8.97mil
Then we can solve the equation that gives differential impedance for S, plug in our values for single-ended and differential impedance and see what trace-spacing (S) we get.
S = -H / 0.96 * ln((2 * Z(single-ended) - Z(differential)) / 0.96 / Z(single-ended)) S(Z(single-ended) = 55 Ohm) = -6.4mil / 0.96 * ln((2 * 55 Ohm - 100 Ohm) / 0.96 / 55 Ohm) = 11.1mil
The distance, D, to adjacent signal pairs and shield traces is suggested to be, D >= 3 * S[12] with the caveat that running a ground shield trace on only one side can create an imbalance that increases EMI. "Ground trace shields should have a scattering of vias to the underlying ground plane."[12]
Z(single-ended) W<mil> S<mil> min{D}<mil> <Ohm> 51 10.2 21.3 63.9 55 8.97 11.1 33.3 60.1 7.58 7.00 21.0 64.6 6.51 5.02 15.1 Table of single-ended impedances and associated trace width and spacing.[These numbers are based on formulas which are approximations with error bounds of +/-10%.][12]
Here we can see the effect of changing the single-ended impedance on width and spacing of traces in a differential pair of given differential impedance. By raising the single-ended impedance we reduced both the width of the traces and also the spacing. The other outgrowth is that the common-mode rejection is improved by lowering the single-ended impedance of the traces. Common-mode signal stems from other signals (EMI) coupled into the traces, uncompensated intra-pair skew, and imperfect differential signal drivers at the source. Common-mode signal will radiate (EMI) from circuit board traces. So we have a trade-off to consider: 1. We can minimize common-mode signal by lowering single-ended impedance which increases the trace width and spacing for a given differential impedance. 2. This is limited by the fact that, for a microstrip differential pair, the single-ended impedance is greater than half the differential impedance.
Looking at the single-ended impedance values, the difference between 51 Ohm and 64.6 Ohm is an increase of less than 30% and thus won't drastically change the common-mode performance, so my inclination if you're strapped for space would be to use the higher single-ended impedance with 6.5mil wide traces spaced apart 5mils and try for 15mils between pairs.
Reviewing with reference to TI's "Routing Guidelines"[20]: i. Use the smallest trace spacing possible, which usually is specified by your PCB vendor: in our case 5 mils ii. Make sure the geometries obey: a. S < H; (S = 5mil) < (H = 6.4mil) b. S < W; (S = 5mil) < (W = 6.5mil) c. W < 2H; (W = 6.5mil) < (2H = 12.8mil) d. D > 2S = 10mil Looks like we abide by their guidelines if we use the 64.6 Ohm single-ended impedance values. It seems the distance, D, to the next trace is somewhat flexible because in this reference it is reduced from 3S to 2S. (I'm sure 3S is better than 2S, if you have the space.)
Ground Planes under Pads
Toradex mentions the lower impedance between wide traces and the reference plane causing impedance mismatch at large pads for components and connectors.[21] The width of the pads in the illustration are 5-6x the width of the traces connecting to them. On the micro-HDMI connector the width of the pads is around 0.2mm (JAE DC3R019JA7R1500 pad width = 0.23 +/-0.03 mm ~= 9.1 +/- 1.1 mil), where the smallest trace we can have is 5 mil thus our greatest proportion is 10.2 mil / 5 mil ~ 2. So this is probably less of a problem than if the pads were 5-6 times the width of our traces. In fact if we compare the dimensions of the connector pads and spacing (which is about the same as pad width) to those of the trace width and spacing for 55 Ohm single-ended impedance in the table above, they nearly match. Thus I don't think this will be a big issue for this board because while the pads are wider than our traces, they're spaced about as far apart as we would space traces that are that wide to still get 100 Ohm differential impedance.
Via Impedance
If and when we start supporting HDMI v2.0+ we will need to tune the impedance of our signal vias even more keenly as our signals will surpass the 10GHz barrier.[22] Presently we also have the happy situation that since our high-frequency signal vias always connect between top and bottom layers, our stub length is 0 on signal vias. Creating transparent (tuned) vias requires familiarity with a 3-D EM simulator and some time to set up, run, evaluate results of simulations, and then repeat in order to tune the impedance. (See section below "Libre Field Solvers".) We can still take some of the recommendations to heart: 1. Use minimal size vias for high-frequency traces to reduce parasitic capacitance.[23] 2. Place the two vias of the differential pair in close proximity to increase capacitive coupling between the signals.(smaller via pitch) 3. Instead of using two separate anti-pads on signal vias, combine them into oval shared antipads (on every layer) to reduce parasitic capacitance. 4. Place ground vias next to signal vias to provide ground-return paths.[22, Figure 2]
References: [1] https://en.wikipedia.org/wiki/FR-4 [2] Toradex, page 21 [3] Toradex, page 38 [4] TI, page 4 [5] Chrontel, page 5 [6] https://forum.allaboutcircuits.com/threads/hdmi-inter-intra-pair-skew-inter-... [7] https://e2e.ti.com/support/interface/high_speed_interface/f/138/t/267205 [8] https://www.researchgate.net/publication/224650488_Effects_of_skew_on_EMI_fo... [9] Toradex, page 17, Figures 12 & 13 [10] Toradex, pages 22-23 [11] Chrontel, page 4 [12] TI, page 5 [13] JAE, page 1 [14] Toradex, page 12 [15] Toradex, page 13, Table 3 [16] http://referencedesigner.com/cal/cal_02.php [17] https://en.wikipedia.org/wiki/Ounce#International_avoirdupois_ounce [18] https://en.wikipedia.org/wiki/Copper [19] https://en.wikipedia.org/wiki/Densities_of_the_elements_(data_page) [20] TI, page 8 [21] Toradex, pages 18-19, Figure 16 [22] https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs... [23] TI, page 9
Bibliography:
Chrontel: Application Note AN-B026, "PCB Layout and Design Guide for CH7101A HDMI to VGA Converter", http://www.chrontel.com/media/Application%20Notes/AN-B026%20Rev0.2.pdf
Japan Aviation Electronics Industry, Ltd. (JAE): "HDMI Standard Type D HDMI Micro Connector: DC3 Series", Connector MB-0233-2, May 2013, http://www.jae.com/z-en/pdf_download_exec.cfm?param=MB-0233-2E_DC3.pdf
Texas Instruments (TI): "HDMI Design Guide", High-Speed Interface Products, June 2007, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/...
Toradex: "Layout Design Guide", v1.0, 14 April 2015, http://docs.toradex.com/102492-layout-design-guide.pdf
On Thu, Aug 3, 2017 at 12:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here we can see the effect of changing the single-ended impedance on width and spacing of traces in a differential pair of given differential impedance. By raising the single-ended impedance we reduced both the width of the traces and also the spacing.
i know from DDR3 that they can change (dynamically) the end-impedance both on the SoC and in the DDR3 RAM ICs. it means you can stick with a particular track width and spacing then have the SoC and DDR3 ICs adjust each end to suit.
Toradex mentions the lower impedance between wide traces and the reference plane causing impedance mismatch at large pads for components and connectors.[21]
yehyeh. fortunately the ones on the DC3 connector are tiny.
i think you're saying we're ok here with 5mil track, 5mil spacing, and lots and lots of ground vias. i can't get them in between the diff-pairs though.
l.
On Thu, Aug 3, 2017 at 7:11 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 3, 2017 at 12:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Here we can see the effect of changing the single-ended impedance on width and spacing of traces in a differential pair of given differential impedance. By raising the single-ended impedance we reduced both the width of the traces and also the spacing.
i know from DDR3 that they can change (dynamically) the end-impedance both on the SoC and in the DDR3 RAM ICs. it means you can stick with a particular track width and spacing then have the SoC and DDR3 ICs adjust each end to suit.
Interesting trick with the SoC and DDR3 RAM ICs. What I was talking about is how we can change the single-ended impedance of our design while holding the differential impedance at 100 Ohm and what effect that has on trace width and spacing. If we reduce the trace width and spacing but maintain 100 Ohm differential impedance, our single-ended impedance goes up! It's not exactly rocket science. When we narrow the traces we have less capacitive coupling to ground so you might expect our single-ended impedance would rise.
Toradex mentions the lower impedance between wide traces and the reference plane causing impedance mismatch at large pads for components and connectors.[21]
yehyeh. fortunately the ones on the DC3 connector are tiny.
i think you're saying we're ok here with 5mil track, 5mil spacing, and lots and lots of ground vias. i can't get them in between the diff-pairs though.
Close. What I am saying is that the DC3 connector pads and spacing actually look pretty close to row 2 of the table (55 Ohm single-ended impedance) for 100 Ohm differential trace geometries. So I don't think the DC3 lands will cause a large impedance discontinuity. In other words no need to obstruct the ground reference plane from under the DC3 lands.
What I said earlier is that I would recommend the following geometry for the transmission lines: trace width = 6.5mil trace spacing = 5mil offset from other copper in the same layer >= 10mil (ground shield trace, other differential pair, etc.)
We'll primarily need ground vias where the signal changes layers and thus the return current needs to change from one ground reference layer to the other. If we do a pretty decent job of squashing the skew and the differential drivers on the chip give us a signal with little common-mode energy to start with, we won't need much of any shielding between pairs. Since the ground shield will be asymmetric (only on one side of a pair) I would recommend keeping it as far away as possible so it will have less asymmetric effect on the impedance.
I have two more sections in mind: Libre Field Solvers and Recommendations (Specific to this Layout). The first is more than half researched and written. I think it can be finished in another couple hours. The second is a little more fluid as I plan to make some recommendations/suggestions and ask some questions which will allow me to refine those recommendations or suggestions.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Aug 3, 2017 at 2:59 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
What I said earlier is that I would recommend the following geometry for the transmission lines: trace width = 6.5mil
there's not enough space. when i said "there's not enough space" i *really meant*, "there's not enough space". it *might* be possible to increase to 5.1 mil but i think you'd agree it would not be worth it.
the reason that there's not enough space is because:
the processor is only about 4.5mm away from the edge of the board. this used to be only 3.5mm.
there is no way to further increase the width of the board.
there is no way that i am moving the processor. or the DDR3 RAM ICs.
the 24mhz XTAL is *right* next to the damn HDMI signals. as it's that close, it blocks layer 1.
moving the XTAL to layer 6 is a bad idea (vias) but even if you did that it *still* would not help... because the PMIC components are in the way on layer 1 further down the board.
the space that would normally be used to drop the HDMI signals onto layer 6 immediately they come out the vias is not available because there are tracks on both layer 3 and layer 6 which are in the way (and cannot be routed anywhere else)
ok i did a video explaining: https://youtu.be/vFbzAmLSHPY
l.
On Thu, Aug 3, 2017 at 9:59 AM, Vincent Legoll vincent.legoll@gmail.com wrote:
does all that means HDMI output will be flakey ?
Not if we creatively approach the problems at hand. In other words we are not quitting, and neither are we finished yet.
On Thu, Aug 3, 2017 at 9:28 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 3, 2017 at 2:59 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
What I said earlier is that I would recommend the following geometry for the transmission lines: trace width = 6.5mil
there's not enough space. when i said "there's not enough space" i *really meant*, "there's not enough space". it *might* be possible to increase to 5.1 mil but i think you'd agree it would not be worth it.
the reason that there's not enough space is because:
[...]
Thanks for the explanation. Sorry, I didn't remember how tight things were. I was thinking about how we now have more space--just not that much more space.
So, I ran some numbers the other direction through the equations to see what impedance we can expect from the connector lands and smaller trace sizes without smaller trace separation:
The good news is it looks like we are still within the +/-15% of 100 Ohm. I'll explain more later.
ok i did a video explaining: https://youtu.be/vFbzAmLSHPY
Thanks for the video, I watched the first 55s and thus this reply. I'll finish watching and then tie up loose ends.
On Thu, Aug 3, 2017 at 8:04 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
The good news is it looks like we are still within the +/-15% of 100 Ohm. I'll explain more later.
ok :)
ok i did a video explaining: https://youtu.be/vFbzAmLSHPY
Thanks for the video, I watched the first 55s and thus this reply. I'll finish watching and then tie up loose ends.
the one thing to remember is, with this track size and separation there _have_ been successful boards... just with different connectors that are no longer available.
most of the video is explaining how it's not possible to move things about. but towards the end (last couple of mins) i focus on the connector, explaining how the vias come up around the diamond-shaped pads.
l.
On Thu, Aug 3, 2017 at 9:28 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Thu, Aug 3, 2017 at 2:59 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
What I said earlier is that I would recommend the following geometry for the transmission lines: trace width = 6.5mil
there's not enough space. when i said "there's not enough space" i *really meant*, "there's not enough space". it *might* be possible to increase to 5.1 mil but i think you'd agree it would not be worth it.
Below find the revised treatment of the latter part of the discussion in light of the facts you enumerated.
""" Turns out there isn't enough room to route 6.5mil traces.
W<mil> S<mil> Z(single-ended) Z(differential) <Ohm> <Ohm> 5 5 72.1 111 5.1 5 71.5 111 5.2 5 71.0 110 *Table* of single-ended and differential impedances for geometries constrained by lack of board space.
These impedances fall in the +/-15% margin of the nominal 100 Ohm differential impedance [85,115]Ohm.
Reviewing with reference to TI's "Routing Guidelines"[20]: i. Use the smallest trace spacing possible, which usually is specified by your PCB vendor: in our case 5 mils ii. Make sure the geometries obey: a. S < H; (S = 5mil) < (H = 6.4mil) b. S < W; (S = 5mil) < (W = 5.1mil) c. W < 2H; (W = 5.1mil) < (2H = 12.8mil) d. D > 2S = 10mil Looks like we abide by their guidelines if we use the 64.6 Ohm single-ended impedance values. Likewise, we can still meet all the margins if we use 5.1mil trace width and 5mil spacing. It seems the distance, D, to the next trace is somewhat flexible because in this reference it is reduced from 3S to 2S. (I'm sure 3S is better than 2S, if you have the space.)
Ground Planes under Pads
Toradex mentions the lower impedance between wide traces and the reference plane causing impedance mismatch at large pads for components and connectors.[21] The width of the pads in the illustration are 5-6x the width of the traces connecting to them. On the micro-HDMI connector the width of the pads is around 0.2mm (JAE DC3R019JA7R1500 pad width = 0.23 +/-0.03 mm ~= 9.1 +/- 1.2 mil), and the pads are lined up on 0.4mm centers. This implies that the spacing is 0.4mm - (0.23 +/-0.03mm) = 0.17 -/+0.03mm ~= 6.7 +/-1.2mil W<mil> S<mil> Z(single-ended) Z(differential) <Ohm> <Ohm> 7.9 5.5 58.9 93.0 [DC3 lands, w-tol, s-tol] 7.9 7.9 58.9 100 [DC3 lands, w-tol, s+tol] 9.1 6.7 54.5 89.9 [DC3 lands, nominal] 10.3 5.5 50.7 80.0 [DC3 lands, w+tol, s-tol] 10.3 7.9 50.7 86.5 [DC3 lands, w+tol, s+tol] *Table* of single-ended and differential impedances for geometries constrained by micro HDMI connector lands.
These differential impedances are all within JAE's 100 Ohm +/-25% = [75,125] Ohm. The best thing to do here would most likely be to ease the transition from the main trace impedance to the connector impedance over a distance. Where they are close to a via, we could ease up to the via width from the normal trace width over a few mil.
Via Impedance
If and when we start supporting HDMI v2.0+ we will need to tune the impedance of our signal vias even more keenly as our signals will surpass the 10GHz barrier.[22] Presently we also have the happy situation that since our high-frequency signal vias always connect between top and bottom layers, our stub length is 0 on signal vias. Creating transparent (tuned) vias requires familiarity with a 3-D EM simulator and some time to set up, run, evaluate results of simulations, and then repeat in order to tune the impedance. (See section below "Libre Field Solvers".)
We can still take some of the recommendations to heart: 1. Use minimal size vias for high-frequency traces to reduce parasitic capacitance.[23] 2. Place the two vias of the differential pair in close proximity to increase capacitive coupling between the signals.(smaller via pitch) 3. Instead of using two separate anti-pads on signal vias, combine them into an oval shared antipad (on every layer) to reduce parasitic capacitance. 4. Place ground vias next to signal vias to provide low-impedance ground-return paths.[22, Figure 2] """
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Thu, Aug 3, 2017 at 11:53 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
We can still take some of the recommendations to heart:
- Use minimal size vias for high-frequency traces to reduce
parasitic capacitance.[23]
yep. 0402 all the way round. can't go smaller as it risks the drill hitting the edge of the ring.
- Place the two vias of the differential pair in close proximity to
increase capacitive coupling between the signals.(smaller via pitch)
yep. doing that.
- Instead of using two separate anti-pads on signal vias, combine
them into an oval shared antipad (on every layer) to reduce parasitic capacitance.
oo. never heard of this practice. never heard of "anti-pads" either! so sorry, if you put some references i missed them.
- Place ground vias next to signal vias to provide low-impedance
ground-return paths.[22, Figure 2]
yep doing that.
l.
2017-08-04 9:19 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 3, 2017 at 11:53 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Instead of using two separate anti-pads on signal vias, combine
them into an oval shared antipad (on every layer) to reduce parasitic capacitance.
oo. never heard of this practice. never heard of "anti-pads" either! so sorry, if you put some references i missed them.
https://e2e.ti.com/cfs-file/__key/communityserver-blogs-components-weblogfil...
From https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
Basically a barrier between a via and a passing layer. Something default to prevent shorting.
With differentals have them combined so there is nothing in between them in a horizontal line/z axis as well.
On Fri, Aug 4, 2017 at 8:51 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-04 9:19 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 3, 2017 at 11:53 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Instead of using two separate anti-pads on signal vias, combine
them into an oval shared antipad (on every layer) to reduce parasitic capacitance.
oo. never heard of this practice. never heard of "anti-pads" either! so sorry, if you put some references i missed them.
https://e2e.ti.com/cfs-file/__key/communityserver-blogs-components-weblogfil...
From https://e2e.ti.com/blogs_/b/analogwire/archive/2015/06/10/differential-pairs...
Basically a barrier between a via and a passing layer. Something default to prevent shorting.
oh, ok - just a hole where you'd expect one to be :) didn't know its name was "anti-pad".
With differentals have them combined so there is nothing in between them in a horizontal line/z axis as well.
turns out that the anti-pads from PADS are big enough to create a figure-8.
l.
On Fri, Aug 4, 2017 at 4:16 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Fri, Aug 4, 2017 at 8:51 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-04 9:19 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
On Thu, Aug 3, 2017 at 11:53 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
- Instead of using two separate anti-pads on signal vias, combine
them into an oval shared antipad (on every layer) to reduce parasitic capacitance.
oo. never heard of this practice. never heard of "anti-pads" either! so sorry, if you put some references i missed them.
[...]
Basically a barrier between a via and a passing layer. Something default to prevent shorting.
oh, ok - just a hole where you'd expect one to be :) didn't know its name was "anti-pad".
Sorry for not explaining very well and no references. Thank you Mike for adding both to the discussion.
With differentals have them combined so there is nothing in between them in a horizontal line/z axis as well.
turns out that the anti-pads from PADS are big enough to create a figure-8.
That's cool. The reason for an oval (or ellipse) shape instead of a figure-8, if you can muster an oval or ellipse, is that the sharp points greatly concentrate electric fields--leading to capacitance--which is pretty much the opposite effect of a smooth curve.
I'm glad to hear that successful HDMI layouts have been achieved using 5mil width, 5mil spacing for differential pairs. The reason I recommended 5.1mil width, 5mil spacing is because TI's geometry recommendation includes the condition width > spacing. Sounds like that is not a necessary condition for a working board.
2017-08-03 17:28 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
ok i did a video explaining: https://youtu.be/vFbzAmLSHPY
Informative. Might I suggest a screen recorder? Although that might be a bit more work in post editing, it might be more clear and .
The middle GND traces could use a bit more riveting(via's). There's space in the corners. The outer HDMI GND trace, on the inner side of the board, might benefit from some riveting like to one on the outer side.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, Aug 4, 2017 at 8:41 AM, mike.valk@gmail.com mike.valk@gmail.com wrote:
2017-08-03 17:28 GMT+02:00 Luke Kenneth Casson Leighton lkcl@lkcl.net:
ok i did a video explaining: https://youtu.be/vFbzAmLSHPY
Informative. Might I suggest a screen recorder? Although that might be a bit more work in post editing, it might be more clear and .
ahh...... this screen's 3000x1800 :)
The middle GND traces could use a bit more riveting(via's). There's space in the corners. The outer HDMI GND trace, on the inner side of the board, might benefit from some riveting like to one on the outer side.
i can get some more in on the right lower side where the traces begin to turn 45 degrees upwards after a long run from the processor - i can't get any on the other side (right upper) because the 1206 capacitors for IPSOUT and 5VIN are in the way.
l.
arm-netbook@lists.phcomp.co.uk
-
Luke Kenneth Casson Leighton -
mike.valk＠gmail.com -
Richard Wilbur -
Vincent Legoll