Working on the high-frequency taper, a couple things have been bothering me--the two ground vias circled in the attached picture. Are they either optional or moveable? If so, even moving them East or Northeast takes some pressure off the taper. If not, we'll work around them but it is a little more complicated.
Richard
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Nov 22, 2017 at 4:55 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Working on the high-frequency taper, a couple things have been bothering me--the two ground vias circled in the attached picture. Are they either optional or moveable?
they're not really optional, they're GNDing VIAs for a couple of capacitors on the TOP layer, associated with the PMIC area. i'll take a look, see what they're for: it *might* be possible to move them direclly south or south east, to the edge of the exclusion area.
also i just noticed that TX1N/P has that little kink, it turns 45 degrees anti-clockwise (from the long horizontal straight) about 15mil late, and i really don't know why :)
If so, even moving them East or Northeast takes some pressure off the taper. If not, we'll work around them but it is a little more complicated.
less complicated is good....
l.
On Nov 22, 2017, at 10:08, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
they're not really optional, they're GNDing VIAs for a couple of capacitors on the TOP layer, associated with the PMIC area. i'll take a look, see what they're for: it *might* be possible to move them direclly south or south east, to the edge of the exclusion area.
If they are grounding power capacitors, don't move them unless you can do so while maintaining (or better yet shrinking) the distance from capacitor pad to via. Low impedance power is precious!
also i just noticed that TX1N/P has that little kink, it turns 45 degrees anti-clockwise (from the long horizontal straight) about 15mil late, and i really don't know why :)
It seems you decided to split up the extra width needed to accommodate the ground vias between TX0 and the clock lines across all the Northeast bends and then move TX1 and TX0 to avoid running into the ground vias. I see both TX1 and TX0 jogging back to 15mil inter-pair (between pair) spacing after they turn Northeast. Had we closely maintained that spacing in the corner, the bends in TX2 would have pointed through the bends in TX1, TX0, and TXC. Actually, the corner in the northern keep away for the ground fill would look through the corners in TX2, TX1, TX0, TXC, and the southern keep away for ground fill.
less complicated is good....
I agree. I try to avoid unneeded complication. Therefore it comes down to balancing priorities: the most important things generally represent "needed" complexity.
Richard
On Wed, Nov 22, 2017 at 6:56 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
If they are grounding power capacitors, don't move them unless you can do so while maintaining (or better yet shrinking) the distance from capacitor pad to via. Low impedance power is precious!
ok :)
also i just noticed that TX1N/P has that little kink, it turns 45 degrees anti-clockwise (from the long horizontal straight) about 15mil late, and i really don't know why :)
It seems you decided to split up the extra width needed to accommodate the ground vias between TX0 and the clock lines across all the Northeast bends and then move TX1 and TX0 to avoid running into the ground vias.
something like that... yeah. i've been experimenting with x11 settings recently so haven't fired up PADS in a while (as X11 crashes terminate the QEMU VM with prejudice, which is bad). i remember that the priority was to get the layer-changing points to be running east-west, because in previous iterations having them run NE<->SW was a disaster. that in turn had knock-on effects back down the line..
l.
http://rhombus-tech.net/allwinner_a10/news/eoma68-a20-275-layers126-illustra...
ok so this shows what's going on: already those GND vias have been moved significantly away from the pads associated with them (the ones for the 5V0) and those are MAJOR power (2A) so it's really rather important to have them close.
now, what i _could_ do is turn the one connected to IPSOUT round by 90 degrees (anti-clockwise) and move it upwards, making use of the GND vias near the HX2P/N diff-pair vias. then there would be room to do the same thing with the 5V0 power in one as well.
one thing: in speaking with mike from the factory, he's been tracking the price of capacitors now, which have showed a FIVE TIMES increase in price over the past six months. 0.1uF, 10uF and 100uF capacitors in particular, the prices have gone INSANE.
the reason?
f*****g apple's f*****g phones.
the response: every supplier in shenzhen is HOARDING supplies and asking FIVE times the normal rate.
this isn't going to calm down any time in the next 6 months: it's going to take apple finishing the insane glut of orders for their latest phone, plus a few months extra, before prices return to normal.
so in the meantime what i think i will do is, put in double batches of *smaller* capacitors, with unusual values (three 33uF instead of one 100uF), which is, from what i've read, a better way to ensure stable power *anyway*.
as in, two 4.7uF capacitors stabilise power much better than one 10uF capacitor because of the increased current capacity of two caps - something like that, anyway.
bottom line: if i shuffle in two 0603 4.7uF caps as a replacement for the 0805 10uF, it reduces the cost on the BOM based on current pricing, improves power stability, and also means that those VIAs in the middle there can entirely be removed.
l.
On Sat, Nov 25, 2017 at 6:15 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
bottom line: if i shuffle in two 0603 4.7uF caps as a replacement for the 0805 10uF, it reduces the cost on the BOM based on current pricing, improves power stability, and also means that those VIAs in the middle there can entirely be removed.
ta-daaaaa :)
Very nicely refactored capacitors! The only thing I am missing is the ground bypass vias close to the TX2 signal vias. I can't see them on the picture you included in the message, at least.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 3:13 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Very nicely refactored capacitors! The only thing I am missing is the ground bypass vias close to the TX2 signal vias. I can't see them on the picture you included in the message, at least.
argh! damnit, this is one of the things that pisses me off about PADS Layout: it occasionally decides, "oh that GND track you just deleted, it's no longer got any purpose... *let's delete it for you*" nggggggh.
well spotted, i'll put it - some... - back.
l.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 3:16 PM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 3:13 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
Very nicely refactored capacitors! The only thing I am missing is the ground bypass vias close to the TX2 signal vias. I can't see them on the picture you included in the message, at least.
argh! damnit, this is one of the things that pisses me off about PADS Layout: it occasionally decides, "oh that GND track you just deleted, it's no longer got any purpose... *let's delete it for you*" nggggggh.
well spotted, i'll put it - some... - back.
grr, about 3 (at least) got deleted. squished them back in between the diffpairs.
so, now those act as helpers for the diff-pairs _and_ also for the main IPSOUT power bus. that's 3 very close by the pair of capacitors, and 2 more within about... 30-40mil, one above, one below.
On Nov 25, 2017, at 08:21, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
grr, about 3 (at least) got deleted. squished them back in between the diffpairs.
so, now those act as helpers for the diff-pairs _and_ also for the main IPSOUT power bus. that's 3 very close by the pair of capacitors, and 2 more within about... 30-40mil, one above, one below. <Untitled.jpg>
Looks great! Now I have to drop out till tonight as I will be spending the day with family. Tonight or tomorrow I'll send a drawing for the taper.
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 4:02 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Nov 25, 2017, at 08:21, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
grr, about 3 (at least) got deleted. squished them back in between the diffpairs.
so, now those act as helpers for the diff-pairs _and_ also for the main IPSOUT power bus. that's 3 very close by the pair of capacitors, and 2 more within about... 30-40mil, one above, one below. <Untitled.jpg>
Looks great! Now I have to drop out till tonight as I will be spending the day with family.
always good...
Tonight or tomorrow I'll send a drawing for the taper.
magic.
ok so this is after flood-fill, remember that GND wires (blue) which are within tthe GND flood-fill (grey) *are* part of the GND plane, PADS just continues to highlight their existence (unnecessarily).
so this gives a clear idea of how the current (arbitrarily-created) tapers look like. there are no tapers and no keepout areas on layer 1, because the clearance to... "stuff" is unavoidably within 5-7mil anyway.
l.
On Nov 25, 2017, at 23:14, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok so this is after flood-fill, remember that GND wires (blue) which are within tthe GND flood-fill (grey) *are* part of the GND plane, PADS just continues to highlight their existence (unnecessarily).
so this gives a clear idea of how the current (arbitrarily-created) tapers look like. there are no tapers and no keepout areas on layer 1, because the clearance to... "stuff" is unavoidably within 5-7mil anyway.
Thanks for the pictures. At the north side of the ESD it looks like something violates the board-level 5mil Cu-Cu clearance but I'm guessing it is actually stray silk screen that just happens to be rendered in the same shade of gray.
On Sun, Nov 26, 2017 at 5:37 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Nov 25, 2017, at 23:14, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
ok so this is after flood-fill, remember that GND wires (blue) which are within tthe GND flood-fill (grey) *are* part of the GND plane, PADS just continues to highlight their existence (unnecessarily).
so this gives a clear idea of how the current (arbitrarily-created) tapers look like. there are no tapers and no keepout areas on layer 1, because the clearance to... "stuff" is unavoidably within 5-7mil anyway.
Thanks for the pictures. At the north side of the ESD it looks like something violates the board-level 5mil Cu-Cu clearance but I'm guessing it is actually stray silk screen that just happens to be rendered in the same shade of gray.
yehyeh no idea why. layer 1 it's in white so is obviously silkscreen. one reason why i like looking at this stuff with gerbv after gerber generation, all the nonsense is gone.
l.
On Saturday, November 25, 2017 01:15:11 AM Luke Kenneth Casson Leighton wrote:
bottom line: if i shuffle in two 0603 4.7uF caps as a replacement for the 0805 10uF, it reduces the cost on the BOM based on current pricing, improves power stability, and also means that those VIAs in the middle there can entirely be removed.
Very nice!
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 1:47 PM, rhkramer@gmail.com wrote:
On Saturday, November 25, 2017 01:15:11 AM Luke Kenneth Casson Leighton wrote:
bottom line: if i shuffle in two 0603 4.7uF caps as a replacement for the 0805 10uF, it reduces the cost on the BOM based on current pricing, improves power stability, and also means that those VIAs in the middle there can entirely be removed.
Very nice!
getting there :)
i was able to take out the double-kink thing on both TX1 and TX0, also out the CK line flat with the 3 data pairs, but of course kinking to go round the TX0 layer-change vias.
also i've just moved the keepout area in as well.
On Nov 24, 2017, at 23:15, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Thank you for the picture.
ok so this shows what's going on: already those GND vias have been moved significantly away from the pads associated with them (the ones for the 5V0) and those are MAJOR power (2A) so it's really rather important to have them close.
Agreed!
now, what i _could_ do is turn the one connected to IPSOUT round by 90 degrees (anti-clockwise) and move it upwards, making use of the GND vias near the HX2P/N diff-pair vias. then there would be room to do the same thing with the 5V0 power in one as well.
Sounds good.
one thing: in speaking with mike from the factory, he's been tracking the price of capacitors now, which have showed a FIVE TIMES increase in price over the past six months. 0.1uF, 10uF and 100uF capacitors in particular, the prices have gone INSANE.
[.…]
Sorry about the demand fluctuation creating such huge price fluctuations.
so in the meantime what i think i will do is, put in double batches of *smaller* capacitors, with unusual values (three 33uF instead of one 100uF), which is, from what i've read, a better way to ensure stable power *anyway*.
as in, two 4.7uF capacitors stabilise power much better than one 10uF capacitor because of the increased current capacity of two caps - something like that, anyway.
Great idea! You are correct in that the real capacitor which we can mount on a circuit board has an equivalent circuit which includes other components to the impedance besides just capacitance. Namely ESR (Equivalent Series Resistance) and inductance. The parasitic resistance dominates low-frequency response while the parasitic inductance dominates high-frequency response. If you have the room, both of these can be combatted by doing just what you have described!
bottom line: if i shuffle in two 0603 4.7uF caps as a replacement for the 0805 10uF, it reduces the cost on the BOM based on current pricing, improves power stability, and also means that those VIAs in the middle there can entirely be removed.
Excellent solution to both problems! Id est, "Good show, mate!"
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Sat, Nov 25, 2017 at 3:05 PM, Richard Wilbur richard.wilbur@gmail.com wrote:
On Nov 24, 2017, at 23:15, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
Sorry about the demand fluctuation creating such huge price fluctuations.
maaad. also the pricing on the DDR3 RAM IC is going nuts, but that's for different reasons: it's getting "old" so not so common any more. i'll need to test some 1866mhz DDR3 RAM ICs, but try them at the 350mhz speed that the layout copes with (safely, and with less power used), see how it goes.
so in the meantime what i think i will do is, put in double batches of *smaller* capacitors, with unusual values (three 33uF instead of one 100uF), which is, from what i've read, a better way to ensure stable power *anyway*.
as in, two 4.7uF capacitors stabilise power much better than one 10uF capacitor because of the increased current capacity of two caps - something like that, anyway.
Great idea! You are correct in that the real capacitor which we can mount on a circuit board has an equivalent circuit which includes other components to the impedance besides just capacitance. Namely ESR (Equivalent Series Resistance) and inductance. The parasitic resistance dominates low-frequency response while the parasitic inductance dominates high-frequency response. f you have the room, both of these can be combatted by doing just what you have described!
:)
arm-netbook@lists.phcomp.co.uk
-
Luke Kenneth Casson Leighton -
rhkramer＠gmail.com -
Richard Wilbur