okaay, so this is what i've managed for the outgoing vias (layer 1), the two lengths are equal (to each other and including across all four pairs) and the relative positions of each via are identical.
for layer 6.... faak it's tight on space down the bottom, so i simply can't get anything but "turns" in. it'll have to go dead-straight until the other end of the board, after the PMIC, where i'll then be able to correct the length differences between the CLK pair and the other pairs.
richard you said that the difference between all pairs should be no more than 100mil, right? but that clock should be a leetle bit longer.
CLK-pairs are 57.245 (i got them to within a thousandth of a mm! 57.245 and 57.24518 how jammy is that!!)
HX2N/P are 49.something - a hell of a big difference. luckily that one's on the outside edge so i can "wiggle" it a lot :)
oh... i had another go at the USB pairs, after reading all that you recommended i wasn't happy that there was skew (which i never noticed before). the USB lines worked but there would have been quite a bit of EM.
l.