On Wed, Aug 30, 2017 at 4:01 AM, Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
On Wed, Aug 30, 2017 at 7:18 AM, Richard Wilbur richard.wilbur@gmail.com wrote:
[...]
mrhm grumble i have to redo those nice length-matchings.... agaaainn aaargh :)
I feel your pain. (I don't know whether this helps, but I've heard it is for a good cause.;>)
or... i _could_ just put in a copper-to-diffpair Design Rule of "15 mil" clearance - that would keep the flood-fill away.
I think this is the most maintainable solution.
ok attached is the result of doing that. layer 1 just after the SoC the "surround" on the vias is well over 15mil away, on *all* layers... including GND. all VIAs are now avoided by the specified 15mil.
... seems a bit much, to me....
This is an attempt to maintain the impedance of the differential pairs to ground which helps reduce the common mode signal (which will radiate as EMI). With re-reading I noticed that the same document from TI ("HDMI Design Guide") which recommends the clearance between differential traces and any copper not a part of that same differential pair be d >= 3s [1] also mentions in the summary of routing guidelines some geometry recommendations among which is d > 2s [2]. In doing some more reading on the subject, a TI High-Frequency Analog design seminar slide mentions that it is common to put ground planes along both sides of the microstrip differential pair but at a larger distance than we have room to accommodate.(width > spacing, d > 2w)[3]
I believe we can abide by all of these constraints at d = 3s. Thus my recommendation to move ground shields on the outside of the pairs to 15mil away from the closest pair and remove the ground shields between the pairs because that will constitute 15mil spacing between pairs.
The seminar notes also suggest vias tying the ground in the signal layer to the ground plane below the differential pair at least every 100mil along the signal path--quite a fence[3]. Obviously, we have to accommodate the signals on other layers, as well.
The images as I received them were named: received saved as ----------- ------------- Untitled3.jpg eoma68_a20_275b_connector_bot.jpg Untitled2.jpg eoma68_a20_275b_processor_top.jpg Untitled1.jpg eoma68_a20_275b_processor_bot.jpg Untitled4.jpg eoma68_a20_275b_processor_gnd.jpg
What I notice in eoma68_a20_275b_connector_bot.jpg is that the ground shield traces and ground vias which violate the 15mil differential-pair-to-anything-else clearance stick out noticeably from the ground fill. For the vias on the edge of the ground fill, one possible solution would be to sneak them back inside the ground fill. For ground vias that we need to be closer to the differential pair traces or shouldn't move for other reasons (lack of space), can we remove the via pad on the layer where they violate the clearance (in this case layer 6)? That would minimize the coupling without changing the connection between other ground layers.
In eoma68_a20_275b_processor_top.jpg, what I see looks good. I like the curves on XN traces and angles on XP since the curves minimize length to make a turn this also reduces the amount of intra-pair skew (and thus how much compensation is required). I notice HTX2N didn't get the same treatment. Is that because HTX2P makes an extra turn on its way to the via?
In regard to eoma68_a20_275b_processor_bot.jpg I notice that Toradex mentions spacing of parallel traces containing the same signal should be >= 4 * trace width.[4] (For us that would be 4*5mil = 20mil.) Thus all their pictures of intra-pair skew compensation don't have parallel sections (unless they are very short like the tricks in figure 31[5]): _ _ _ _/ _/
or _ _ _/ _/ _
instead of _ _ \ / | | <---parallel sections of same signal _/
They reserve parallel sections of same signal for large meanders involved in inter-pair (between pairs) skew compensation.
I would try and move the bottom ground shield trace (and associated fence vias) down 1mil so that the trace attains the 15mil clearance with HTXCN.
Again, the ground vias and ground shield traces that are closer than 15mil to differential traces and can be moved to respect that boundary would help improve the symmetry and keep the impedance up.
Specifically, the ground shield trace just north of the signal vias which land the signals on layer 6, could move up parallel with the north edge of the adjacent ground fill. Likewise the ground shield trace on the west side of HTXCN could move even with the edge of the ground fill on that side.
My name for eoma68_a20_275b_processor_gnd.jpg is a hypothesis as to what I guess this is a picture of--one of the ground planes over the top layer adjacent to the processor where the signal vias carry the signal from top to bottom. Is that a correct hypothesis?
The keep outs look good from a signal impedance standpoint. It looks like there is no pad on this layer (ground?) on the vias and the 15mil clearance rule is having the expected effect. What did this part of this layer look like before we instituted the 15mil clearance rule? What clearance did we have before? Specifically, did we already have a hole extending over all the signal vias' keep outs or were there fingers of ground that made it between (preferably connecting north to south)?
I don't especially like making such a large hole in the ground plane. If it were only one of two ground planes with that hole I wouldn't worry about it at all. This is both planes plus the power plane. So let's consider it for a moment. Please correct any errors of fact or perspective, below. 1. Each HDMI differential signal via is composed of a 6mil diameter plated-through hole and pads on appropriate layers. 2. The clearance imposes a 15mil radius around the hole = 36mil void in non-signal layer. (This then happens in power and both ground planes.) 3. The return current (from common mode signal) wants to follow the signal in relatively low impedance back to the signal source/driver which implies a power or ground pin of the driver close to the signal pin. Where are the power and ground pins on the SoC relative to the HDMI signal pins? Does the SoC have both positive and negative supply connections (e.g. +3.3V, -3.3V)? Are any of the pins suggestively named such as: VHDMI+, VHDMI- or VDIFF+, VDIFF-? 4. The return current will detour as needed (but it raises the impedance of the path). Probably want to keep the detours down to ~200mil. 5. Where on ground and power planes is the power flow most apparent? (Are we blocking the direct path for any high-power flow? Where are the power sources?[voltage convertors/regulators] Where are the power sinks?[users of power: SoC, etc.])
References:
[1] TI HDMI, p. 5.2 [2] TI HDMI, p. 8, #10 [3] TI Analog, p. 14, beware: they label dimensions differently [4] Toradex, page 17, section 6.2 [5] Toradex, page 25, figure 31
Bibliography:
Texas Instruments (TI HDMI): "HDMI Design Guide", High-Speed Interface Products, June 2007, http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/...
Texas Instruments (TI Analog): "Section 5: High Speed PCB Layout Techniques", High Speed Analog Design and Application Seminar, Date?, http://www.ti.com/lit/ml/slyp173/slyp173.pdf
Toradex: "Layout Design Guide", v1.0, 14 April 2015, http://docs.toradex.com/102492-layout-design-guide.pdf